ERSFQ 8-Bit Parallel Arithmetic Logic Unit

We have designed and tested a parallel 8-bit ERSFQ arithmetic logic unit (ALU). The ALU design employs wave-pipelined instruction execution and features modular bit-slice architecture that is easily extendable to any number of bits and adaptable to current recycling. A carry signal synchronized with...

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Veröffentlicht in:	IEEE transactions on applied superconductivity 2019-08, Vol.29 (5), p.1-7
Hauptverfasser:	Kirichenko, Alex F., Vernik, Igor V., Kamkar, Michael Y., Walter, Jason, Miller, Maximilian, Albu, Lucian Remus, Mukhanov, Oleg A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Arithmetic and logic units Bias Clock generators Clocks Design for recycling digital processing Energy-efficient computation ERSFQ High frequencies Inductance Josephson junctions Low speed Pipelines SFQ superconducting Superconducting logic circuits Switches Synchronization Technology assessment Testing Wave propagation Wiring
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