Fabrication of Superconductor Integrated Circuits of D-Band Dual-Polarization Balanced SIS Mixers
We have fabricated prototype superconductor integrated circuits (ICs), which accommodate planar orthomode transducer (OMT) and balanced superconductor-insulator-superconductor (SIS) mixers operating at D-band (125-163 GHz). The fabrication of the ICs is different from the conventional SIS mixer fabr...
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Veröffentlicht in: | IEEE transactions on applied superconductivity 2019-08, Vol.29 (5), p.1-5 |
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creator | Ezaki, Shohei Shan, Wenlei Asayama, Shin'ichiro Noguchi, Takashi |
description | We have fabricated prototype superconductor integrated circuits (ICs), which accommodate planar orthomode transducer (OMT) and balanced superconductor-insulator-superconductor (SIS) mixers operating at D-band (125-163 GHz). The fabrication of the ICs is different from the conventional SIS mixer fabrication process in several aspects because of new features and components being introduced and incorporated. In particular, very flat silicon membranes that mechanically support the planar OMT and the waveguide probes for local oscillator coupling were formed with a combination of dry and wet etching methods to completely remove the handle layer and the buried oxide layer of the silicon on insulator substrates. We also applied an anodization passivation of the surface of the ground plane and a via-hole etching process with an i-line stepper in the formation of low-leakage SIS junctions. The SIS junctions of moderately good quality have been fabricated with an average quality factor as high as 18, which indicate the integrity of the junction definition with the complex fabrication of ICs. |
doi_str_mv | 10.1109/TASC.2019.2902985 |
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The fabrication of the ICs is different from the conventional SIS mixer fabrication process in several aspects because of new features and components being introduced and incorporated. In particular, very flat silicon membranes that mechanically support the planar OMT and the waveguide probes for local oscillator coupling were formed with a combination of dry and wet etching methods to completely remove the handle layer and the buried oxide layer of the silicon on insulator substrates. We also applied an anodization passivation of the surface of the ground plane and a via-hole etching process with an i-line stepper in the formation of low-leakage SIS junctions. The SIS junctions of moderately good quality have been fabricated with an average quality factor as high as 18, which indicate the integrity of the junction definition with the complex fabrication of ICs.</description><identifier>ISSN: 1051-8223</identifier><identifier>EISSN: 1558-2515</identifier><identifier>DOI: 10.1109/TASC.2019.2902985</identifier><identifier>CODEN: ITASE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Coplanar waveguides ; Dual polarization (waves) ; Etching ; Fabrication ; Ground plane ; Integrated circuits ; Junctions ; Mixers ; Multi-beam heterodyne receiver ; Q factors ; Silicon ; silicon membrane ; Silicon substrates ; SIS (superconductors) ; superconductor integrated circuits ; superconductor-insulator-superconductor mixer</subject><ispartof>IEEE transactions on applied superconductivity, 2019-08, Vol.29 (5), p.1-5</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-d15fcaeef05ec979833dc71e6a34337167240c7deef653ee0c219fc61c1635f33</citedby><cites>FETCH-LOGICAL-c359t-d15fcaeef05ec979833dc71e6a34337167240c7deef653ee0c219fc61c1635f33</cites><orcidid>0000-0003-0298-5512 ; 0000-0003-4035-2513 ; 0000-0002-0009-0363</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8658137$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8658137$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ezaki, Shohei</creatorcontrib><creatorcontrib>Shan, Wenlei</creatorcontrib><creatorcontrib>Asayama, Shin'ichiro</creatorcontrib><creatorcontrib>Noguchi, Takashi</creatorcontrib><title>Fabrication of Superconductor Integrated Circuits of D-Band Dual-Polarization Balanced SIS Mixers</title><title>IEEE transactions on applied superconductivity</title><addtitle>TASC</addtitle><description>We have fabricated prototype superconductor integrated circuits (ICs), which accommodate planar orthomode transducer (OMT) and balanced superconductor-insulator-superconductor (SIS) mixers operating at D-band (125-163 GHz). The fabrication of the ICs is different from the conventional SIS mixer fabrication process in several aspects because of new features and components being introduced and incorporated. In particular, very flat silicon membranes that mechanically support the planar OMT and the waveguide probes for local oscillator coupling were formed with a combination of dry and wet etching methods to completely remove the handle layer and the buried oxide layer of the silicon on insulator substrates. We also applied an anodization passivation of the surface of the ground plane and a via-hole etching process with an i-line stepper in the formation of low-leakage SIS junctions. The SIS junctions of moderately good quality have been fabricated with an average quality factor as high as 18, which indicate the integrity of the junction definition with the complex fabrication of ICs.</description><subject>Coplanar waveguides</subject><subject>Dual polarization (waves)</subject><subject>Etching</subject><subject>Fabrication</subject><subject>Ground plane</subject><subject>Integrated circuits</subject><subject>Junctions</subject><subject>Mixers</subject><subject>Multi-beam heterodyne receiver</subject><subject>Q factors</subject><subject>Silicon</subject><subject>silicon membrane</subject><subject>Silicon substrates</subject><subject>SIS (superconductors)</subject><subject>superconductor integrated circuits</subject><subject>superconductor-insulator-superconductor mixer</subject><issn>1051-8223</issn><issn>1558-2515</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kFFLwzAUhYMoOKc_QHwp-NyZmzRt8rhVp4OJQudziOmtZNR2Ji2ov96WDp_uefjOufARcg10AUDV3W5Z5AtGQS2YokxJcUJmIISMmQBxOmQqIJaM8XNyEcKeUkhkImbErM27d9Z0rm2itoqK_oDetk3Z26710abp8MObDssod972rgsjdR-vTFNG972p49e2Nt79TgsrU5vGDnSxKaJn940-XJKzytQBr453Tt7WD7v8Kd6-PG7y5Ta2XKguLkFU1iBWVKBVmZKclzYDTA1POM8gzVhCbVYORCo4IrUMVGVTsJByUXE-J7fT7sG3Xz2GTu_b3jfDS80YpZJxGIpzAhNlfRuCx0ofvPs0_kcD1aNJPZrUo0l9NDl0bqaOQ8R_XqZCAs_4H07Ub1I</recordid><startdate>20190801</startdate><enddate>20190801</enddate><creator>Ezaki, Shohei</creator><creator>Shan, Wenlei</creator><creator>Asayama, Shin'ichiro</creator><creator>Noguchi, Takashi</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0298-5512</orcidid><orcidid>https://orcid.org/0000-0003-4035-2513</orcidid><orcidid>https://orcid.org/0000-0002-0009-0363</orcidid></search><sort><creationdate>20190801</creationdate><title>Fabrication of Superconductor Integrated Circuits of D-Band Dual-Polarization Balanced SIS Mixers</title><author>Ezaki, Shohei ; Shan, Wenlei ; Asayama, Shin'ichiro ; Noguchi, Takashi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-d15fcaeef05ec979833dc71e6a34337167240c7deef653ee0c219fc61c1635f33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Coplanar waveguides</topic><topic>Dual polarization (waves)</topic><topic>Etching</topic><topic>Fabrication</topic><topic>Ground plane</topic><topic>Integrated circuits</topic><topic>Junctions</topic><topic>Mixers</topic><topic>Multi-beam heterodyne receiver</topic><topic>Q factors</topic><topic>Silicon</topic><topic>silicon membrane</topic><topic>Silicon substrates</topic><topic>SIS (superconductors)</topic><topic>superconductor integrated circuits</topic><topic>superconductor-insulator-superconductor mixer</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ezaki, Shohei</creatorcontrib><creatorcontrib>Shan, Wenlei</creatorcontrib><creatorcontrib>Asayama, Shin'ichiro</creatorcontrib><creatorcontrib>Noguchi, Takashi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005–Present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on applied superconductivity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ezaki, Shohei</au><au>Shan, Wenlei</au><au>Asayama, Shin'ichiro</au><au>Noguchi, Takashi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Fabrication of Superconductor Integrated Circuits of D-Band Dual-Polarization Balanced SIS Mixers</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>2019-08-01</date><risdate>2019</risdate><volume>29</volume><issue>5</issue><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>We have fabricated prototype superconductor integrated circuits (ICs), which accommodate planar orthomode transducer (OMT) and balanced superconductor-insulator-superconductor (SIS) mixers operating at D-band (125-163 GHz). The fabrication of the ICs is different from the conventional SIS mixer fabrication process in several aspects because of new features and components being introduced and incorporated. In particular, very flat silicon membranes that mechanically support the planar OMT and the waveguide probes for local oscillator coupling were formed with a combination of dry and wet etching methods to completely remove the handle layer and the buried oxide layer of the silicon on insulator substrates. We also applied an anodization passivation of the surface of the ground plane and a via-hole etching process with an i-line stepper in the formation of low-leakage SIS junctions. The SIS junctions of moderately good quality have been fabricated with an average quality factor as high as 18, which indicate the integrity of the junction definition with the complex fabrication of ICs.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TASC.2019.2902985</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0003-0298-5512</orcidid><orcidid>https://orcid.org/0000-0003-4035-2513</orcidid><orcidid>https://orcid.org/0000-0002-0009-0363</orcidid></addata></record> |
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subjects | Coplanar waveguides Dual polarization (waves) Etching Fabrication Ground plane Integrated circuits Junctions Mixers Multi-beam heterodyne receiver Q factors Silicon silicon membrane Silicon substrates SIS (superconductors) superconductor integrated circuits superconductor-insulator-superconductor mixer |
title | Fabrication of Superconductor Integrated Circuits of D-Band Dual-Polarization Balanced SIS Mixers |
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