A 125-ps 8-18-GHz CMOS Integrated Delay Circuit

A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125- and 3.9-ps delay resolution, designed and fabricated in a 0.18- \mu \text{m} CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay bl...

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