Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read-Write Operations
With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MR...
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| Veröffentlicht in: | IEEE transactions on magnetics 2019-01, Vol.55 (1), p.1-10 |
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| creator | Prajapati, Sanjay Kaushik, Brajesh Kumar |
| description | With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read-write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below 10^{-9} , and average write energy |
| doi_str_mv | 10.1109/TMAG.2018.2875885 |
| format | Article |
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However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read-write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below <inline-formula> <tex-math notation="LaTeX">10^{-9} </tex-math></inline-formula>, and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F 2 per bit (F is the feature size).</description><identifier>ISSN: 0018-9464</identifier><identifier>EISSN: 1941-0069</identifier><identifier>DOI: 10.1109/TMAG.2018.2875885</identifier><identifier>CODEN: IEMGAQ</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Anisotropic magnetoresistance ; Computer architecture ; Computer memory ; Demagnetization ; Density ; Energy management ; Gate-all-around (GAA) ; Logic gates ; Magnetic anisotropy ; Magnetic tunneling ; Magnetism ; multilevel cell (MLC) ; Nanowires ; Perpendicular magnetic anisotropy ; perpendicular magnetic anisotropy (PMA) ; Power management ; Random access memory ; spin-transfer torque (STT) ; Switches ; Tunnel junctions</subject><ispartof>IEEE transactions on magnetics, 2019-01, Vol.55 (1), p.1-10</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The results of 2 bit sMLC designs demonstrate switching error probability much below <inline-formula> <tex-math notation="LaTeX">10^{-9} </tex-math></inline-formula>, and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F 2 per bit (F is the feature size).</description><subject>Anisotropic magnetoresistance</subject><subject>Computer architecture</subject><subject>Computer memory</subject><subject>Demagnetization</subject><subject>Density</subject><subject>Energy management</subject><subject>Gate-all-around (GAA)</subject><subject>Logic gates</subject><subject>Magnetic anisotropy</subject><subject>Magnetic tunneling</subject><subject>Magnetism</subject><subject>multilevel cell (MLC)</subject><subject>Nanowires</subject><subject>Perpendicular magnetic anisotropy</subject><subject>perpendicular magnetic anisotropy (PMA)</subject><subject>Power management</subject><subject>Random access memory</subject><subject>spin-transfer torque (STT)</subject><subject>Switches</subject><subject>Tunnel junctions</subject><issn>0018-9464</issn><issn>1941-0069</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kN9LwzAQx4MoOKd_gPgS8LkzlyZd8ljGnMLKYKv4Zknbq2R07Uw6Yf71Zkx8Ou7u-70fH0LugU0AmH7Ks3Qx4QzUhKupVEpekBFoARFjib4kIxZakRaJuCY33m9DKiSwEflIHRpquprOO3SfRzpvGltZ7Aa6QWfR0-zQDrbFb2zpDNuWbvI8ytZp5mnTO7raD3Znf7CmazR19O7sgKGIzgy27_wtuWpM6_HuL47J2_M8n71Ey9XidZYuo4rreIhEWUIMzEiuKplIAUlpAI3SCSBLhOKqNmXNOQ_P1FriVGCloFIlaDltmIjH5PE8d-_6rwP6odj2B9eFlQUHqWMlmWJBBWdV5XrvHTbF3tmdcccCWHHCWJwwFieMxR_G4Hk4eywi_utVuJFpHf8CLdlsjg</recordid><startdate>201901</startdate><enddate>201901</enddate><creator>Prajapati, Sanjay</creator><creator>Kaushik, Brajesh Kumar</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read-write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. 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| source | IEEE Electronic Library (IEL) |
| subjects | Anisotropic magnetoresistance Computer architecture Computer memory Demagnetization Density Energy management Gate-all-around (GAA) Logic gates Magnetic anisotropy Magnetic tunneling Magnetism multilevel cell (MLC) Nanowires Perpendicular magnetic anisotropy perpendicular magnetic anisotropy (PMA) Power management Random access memory spin-transfer torque (STT) Switches Tunnel junctions |
| title | Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read-Write Operations |
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