All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply
In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel s...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 2018-12, Vol.53 (12), p.3660-3671 |
|---|---|
| Hauptverfasser: | , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 3671 |
|---|---|
| container_issue | 12 |
| container_start_page | 3660 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 53 |
| creator | Li, Chao-Chieh Yuan, Min-Shueh Liao, Chia-Chun Lin, Yu-Tso Chang, Chih-Hsien Staszewski, Robert Bogdan |
| description | In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes |
| doi_str_mv | 10.1109/JSSC.2018.2871632 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_8490904</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8490904</ieee_id><sourcerecordid>2159388642</sourcerecordid><originalsourceid>FETCH-LOGICAL-c359t-66c62c7cd666d77aed2ab210584cc23d767f8c5bc62d3dbbcf95884cf4e6455c3</originalsourceid><addsrcrecordid>eNo9kM1Kw0AURgdRsFYfQNwMuJ44_zNZ1lqtElCsFVeGZDKpaWMmThKkvoHv4ZP5JKa0uLpcvvPdCweAU4IDQnB4cTebjQOKiQ6oVkQyugcGRAiNiGIv-2CA-wiFFONDcNQ0y37lXJMBeB2VJboqFkWblPAhimDuPLwsO9s6177ByH3CSWX9Yg3nTVEtIKOBkhqtpl_w0ebW28pYOC6dWcGkyuDv9w8OuEDPcNbVdbk-Bgd5Ujb2ZDeHYH49eRpPUXR_czseRcgwEbZISiOpUSaTUmZKJTajSUoJFpobQ1mmpMq1EWlPZSxLU5OHQvdZzq3kQhg2BOfbu7V3H51t2njpOl_1L2NKRMi0lpz2FNlSxrum8TaPa1-8J34dExxvNMYbjfFGY7zT2HfOtp3CWvvPax7iEHP2B6tUbJ8</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2159388642</pqid></control><display><type>article</type><title>All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply</title><source>IEEE Electronic Library (IEL)</source><creator>Li, Chao-Chieh ; Yuan, Min-Shueh ; Liao, Chia-Chun ; Lin, Yu-Tso ; Chang, Chih-Hsien ; Staszewski, Robert Bogdan</creator><creatorcontrib>Li, Chao-Chieh ; Yuan, Min-Shueh ; Liao, Chia-Chun ; Lin, Yu-Tso ; Chang, Chih-Hsien ; Staszewski, Robert Bogdan</creatorcontrib><description>In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes <1 mW at ≤0.45 V, while achieving best-in-class performance and <100-ns hopping time.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2018.2871632</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>All-digital phase-locked loop (ADPLL) ; Bluetooth ; Bluetooth low energy (BLE) ; channel hopping ; Clocks ; Crystal oscillators ; digitally controlled oscillator (DCO) ; FinFET ; FinFETs ; Frequency ranges ; Frequency shift keying ; Modulation ; Oscillators ; Phase locked loops ; Phase locked systems ; Radio frequency ; real-time clock (RTC) ; Settling ; Transceivers ; Transfer functions ; voltage doubler</subject><ispartof>IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3660-3671</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-66c62c7cd666d77aed2ab210584cc23d767f8c5bc62d3dbbcf95884cf4e6455c3</citedby><cites>FETCH-LOGICAL-c359t-66c62c7cd666d77aed2ab210584cc23d767f8c5bc62d3dbbcf95884cf4e6455c3</cites><orcidid>0000-0003-4902-1358 ; 0000-0001-9848-1129</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8490904$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8490904$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Li, Chao-Chieh</creatorcontrib><creatorcontrib>Yuan, Min-Shueh</creatorcontrib><creatorcontrib>Liao, Chia-Chun</creatorcontrib><creatorcontrib>Lin, Yu-Tso</creatorcontrib><creatorcontrib>Chang, Chih-Hsien</creatorcontrib><creatorcontrib>Staszewski, Robert Bogdan</creatorcontrib><title>All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes <1 mW at ≤0.45 V, while achieving best-in-class performance and <100-ns hopping time.</description><subject>All-digital phase-locked loop (ADPLL)</subject><subject>Bluetooth</subject><subject>Bluetooth low energy (BLE)</subject><subject>channel hopping</subject><subject>Clocks</subject><subject>Crystal oscillators</subject><subject>digitally controlled oscillator (DCO)</subject><subject>FinFET</subject><subject>FinFETs</subject><subject>Frequency ranges</subject><subject>Frequency shift keying</subject><subject>Modulation</subject><subject>Oscillators</subject><subject>Phase locked loops</subject><subject>Phase locked systems</subject><subject>Radio frequency</subject><subject>real-time clock (RTC)</subject><subject>Settling</subject><subject>Transceivers</subject><subject>Transfer functions</subject><subject>voltage doubler</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1Kw0AURgdRsFYfQNwMuJ44_zNZ1lqtElCsFVeGZDKpaWMmThKkvoHv4ZP5JKa0uLpcvvPdCweAU4IDQnB4cTebjQOKiQ6oVkQyugcGRAiNiGIv-2CA-wiFFONDcNQ0y37lXJMBeB2VJboqFkWblPAhimDuPLwsO9s6177ByH3CSWX9Yg3nTVEtIKOBkhqtpl_w0ebW28pYOC6dWcGkyuDv9w8OuEDPcNbVdbk-Bgd5Ujb2ZDeHYH49eRpPUXR_czseRcgwEbZISiOpUSaTUmZKJTajSUoJFpobQ1mmpMq1EWlPZSxLU5OHQvdZzq3kQhg2BOfbu7V3H51t2njpOl_1L2NKRMi0lpz2FNlSxrum8TaPa1-8J34dExxvNMYbjfFGY7zT2HfOtp3CWvvPax7iEHP2B6tUbJ8</recordid><startdate>20181201</startdate><enddate>20181201</enddate><creator>Li, Chao-Chieh</creator><creator>Yuan, Min-Shueh</creator><creator>Liao, Chia-Chun</creator><creator>Lin, Yu-Tso</creator><creator>Chang, Chih-Hsien</creator><creator>Staszewski, Robert Bogdan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-4902-1358</orcidid><orcidid>https://orcid.org/0000-0001-9848-1129</orcidid></search><sort><creationdate>20181201</creationdate><title>All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply</title><author>Li, Chao-Chieh ; Yuan, Min-Shueh ; Liao, Chia-Chun ; Lin, Yu-Tso ; Chang, Chih-Hsien ; Staszewski, Robert Bogdan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-66c62c7cd666d77aed2ab210584cc23d767f8c5bc62d3dbbcf95884cf4e6455c3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>All-digital phase-locked loop (ADPLL)</topic><topic>Bluetooth</topic><topic>Bluetooth low energy (BLE)</topic><topic>channel hopping</topic><topic>Clocks</topic><topic>Crystal oscillators</topic><topic>digitally controlled oscillator (DCO)</topic><topic>FinFET</topic><topic>FinFETs</topic><topic>Frequency ranges</topic><topic>Frequency shift keying</topic><topic>Modulation</topic><topic>Oscillators</topic><topic>Phase locked loops</topic><topic>Phase locked systems</topic><topic>Radio frequency</topic><topic>real-time clock (RTC)</topic><topic>Settling</topic><topic>Transceivers</topic><topic>Transfer functions</topic><topic>voltage doubler</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Li, Chao-Chieh</creatorcontrib><creatorcontrib>Yuan, Min-Shueh</creatorcontrib><creatorcontrib>Liao, Chia-Chun</creatorcontrib><creatorcontrib>Lin, Yu-Tso</creatorcontrib><creatorcontrib>Chang, Chih-Hsien</creatorcontrib><creatorcontrib>Staszewski, Robert Bogdan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, Chao-Chieh</au><au>Yuan, Min-Shueh</au><au>Liao, Chia-Chun</au><au>Lin, Yu-Tso</au><au>Chang, Chih-Hsien</au><au>Staszewski, Robert Bogdan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2018-12-01</date><risdate>2018</risdate><volume>53</volume><issue>12</issue><spage>3660</spage><epage>3671</epage><pages>3660-3671</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>In this paper, we introduce an all-digital phase-locked loop (ADPLL) for Bluetooth low energy (BLE) that eliminates the need for a crystal oscillator (XO) other than a 32.768-kHz real-time clock (RTC) already present in wireless systems. Specifically, we propose to replace the conventional channel settling with a band settling that would be carried out only once per global device power up. The ADPLL locks to the center of the Bluetooth band (2440 MHz) upon system power-up and jointly performs an instantaneous channel hopping and Gaussian frequency shift keying (GFSK) modulation in a two-point manner to overcome the narrow PLL bandwidth (BW) due to the 32.768-kHz reference. Extensive calibrations linearize the effective cubic digitally controlled oscillator (DCO) transfer function to achieve a precise frequency range of hopping and modulation. Realized in 16-nm FinFET, it consumes <1 mW at ≤0.45 V, while achieving best-in-class performance and <100-ns hopping time.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2018.2871632</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-4902-1358</orcidid><orcidid>https://orcid.org/0000-0001-9848-1129</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3660-3671 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_8490904 |
| source | IEEE Electronic Library (IEL) |
| subjects | All-digital phase-locked loop (ADPLL) Bluetooth Bluetooth low energy (BLE) channel hopping Clocks Crystal oscillators digitally controlled oscillator (DCO) FinFET FinFETs Frequency ranges Frequency shift keying Modulation Oscillators Phase locked loops Phase locked systems Radio frequency real-time clock (RTC) Settling Transceivers Transfer functions voltage doubler |
| title | All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T18%3A13%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=All-Digital%20PLL%20for%20Bluetooth%20Low%20Energy%20Using%2032.768-kHz%20Reference%20Clock%20and%20%E2%89%A40.45-V%20Supply&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Li,%20Chao-Chieh&rft.date=2018-12-01&rft.volume=53&rft.issue=12&rft.spage=3660&rft.epage=3671&rft.pages=3660-3671&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/JSSC.2018.2871632&rft_dat=%3Cproquest_RIE%3E2159388642%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2159388642&rft_id=info:pmid/&rft_ieee_id=8490904&rfr_iscdi=true |