A cost effective embedded DRAM integration for high density memory and high performance logic using 0.15 /spl mu/m technology node and beyond

In this paper, a 0.15 /spl mu/m embedded DRAM technology is described which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity, and a small foot print chip. The key technologies for high performance transistors are dual thickness gate oxide, dual work-function gate with Si/sub 3/N/sub 4/ capped Ti polycide, and selective Co silicidation of source/drain diffusion by Si/sub 3/N/sub 4/ liner. In order to increase the memory cell efficiency, all memory cell contacts in DRAM arrays are formed by self-aligned contact (SAC) etching. Low temperature Al/sub 2/O/sub 3/ stacked cell capacitor with hemispherical grain (HSG) makes it possible to realize the sufficient storage capacitance in DRAM arrays and the high performance transistor. The CMP planarization of interlayer dielectric enlarges the depth of focus for lithography and enables the multilevel metallization. These integration technologies can be fairly extendible to the future embedded DRAM in 0.13 /spl mu/m technology node and beyond.