A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for re...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2018-11, Vol.26 (11), p.2335-2344 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | Yabuuchi, Makoto Tsukamoto, Yasumasa Fujiwara, Hidehiro Tanaka, Miki Shinji, Shinji Nii, Koji |
| description | We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage ( V_{\text {min}} ) can be reproduced by our test circuit. Bit density of 3.16 Mb/mm 2 was achieved. |
| doi_str_mv | 10.1109/TVLSI.2018.2864267 |
| format | Article |
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To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test circuit for read disturbance and wordline coupling noise. A 512-kbit 2P SRAM macro using 28-nm high-K/metal gate bulk CMOS technology has been designed, confirming experimentally that the worst minimum operation voltage (<inline-formula> <tex-math notation="LaTeX">V_{\text {min}} </tex-math></inline-formula>) can be reproduced by our test circuit. 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| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2335-2344 |
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| source | IEEE Electronic Library (IEL) |
| subjects | 1-read/1-write (1R1W) Circuits CMOS Coupling Couplings Degradation Electric potential Logic gates Monte Carlo methods Random access memory read disturbance Screening screening test circuit Sense amplifiers Static random access memory Testability Timing two-port (2P) static random access memory Very large scale integration wordline (WL) coupling noise |
| title | A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures |
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