Multiple-fault detection for the balanced and unbalanced conditional-sum adders

Multiple-fault detection for the balanced and unbalanced conditional-sum adders

In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be appl...

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Hauptverfasser: Arjhan, C., Deshmukh, R.G.
Format: Tagungsbericht
Sprache:eng
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Computer science
Delay
Electrical fault detection
Fault detection
Robustness
Testing
Upper bound
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description In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed.
doi_str_mv 10.1109/SECON.2000.845593
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_845593</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>845593</ieee_id><sourcerecordid>845593</sourcerecordid><originalsourceid>FETCH-ieee_primary_8455933</originalsourceid><addsrcrecordid>eNp9jrEKwjAYhAMiKNoH0Ckv0Jo0rW3mUnHRDrqX2PzFSJqWJB18eyuKo3Bwd3w3HEIbSiJKCd9dyqI6RzEhJMqTNOVshgKe5WQS2zMakwUKnHtMnCRpkvFsiarTqL0aNIStmBKW4KHxqje47S32d8A3oYVpQGJhJB7Nrza9keq9FDp0Y4eFlGDdGs1boR0EX1-h7aG8FsdQAUA9WNUJ-6w_79hf-ALfXD8Q</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Multiple-fault detection for the balanced and unbalanced conditional-sum adders</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Arjhan, C. ; Deshmukh, R.G.</creator><creatorcontrib>Arjhan, C. ; Deshmukh, R.G.</creatorcontrib><description>In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed.</description><identifier>ISBN: 9780780363120</identifier><identifier>ISBN: 0780363124</identifier><identifier>DOI: 10.1109/SECON.2000.845593</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer science ; Delay ; Electrical fault detection ; Fault detection ; Robustness ; Testing ; Upper bound</subject><ispartof>Proceedings of the IEEE SoutheastCon 2000. 'Preparing for The New Millennium' (Cat. No.00CH37105), 2000, p.359-364</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/845593$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/845593$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Arjhan, C.</creatorcontrib><creatorcontrib>Deshmukh, R.G.</creatorcontrib><title>Multiple-fault detection for the balanced and unbalanced conditional-sum adders</title><title>Proceedings of the IEEE SoutheastCon 2000. 'Preparing for The New Millennium' (Cat. No.00CH37105)</title><addtitle>SECON</addtitle><description>In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed.</description><subject>Computer science</subject><subject>Delay</subject><subject>Electrical fault detection</subject><subject>Fault detection</subject><subject>Robustness</subject><subject>Testing</subject><subject>Upper bound</subject><isbn>9780780363120</isbn><isbn>0780363124</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jrEKwjAYhAMiKNoH0Ckv0Jo0rW3mUnHRDrqX2PzFSJqWJB18eyuKo3Bwd3w3HEIbSiJKCd9dyqI6RzEhJMqTNOVshgKe5WQS2zMakwUKnHtMnCRpkvFsiarTqL0aNIStmBKW4KHxqje47S32d8A3oYVpQGJhJB7Nrza9keq9FDp0Y4eFlGDdGs1boR0EX1-h7aG8FsdQAUA9WNUJ-6w_79hf-ALfXD8Q</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Arjhan, C.</creator><creator>Deshmukh, R.G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2000</creationdate><title>Multiple-fault detection for the balanced and unbalanced conditional-sum adders</title><author>Arjhan, C. ; Deshmukh, R.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_8455933</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Computer science</topic><topic>Delay</topic><topic>Electrical fault detection</topic><topic>Fault detection</topic><topic>Robustness</topic><topic>Testing</topic><topic>Upper bound</topic><toplevel>online_resources</toplevel><creatorcontrib>Arjhan, C.</creatorcontrib><creatorcontrib>Deshmukh, R.G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Arjhan, C.</au><au>Deshmukh, R.G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Multiple-fault detection for the balanced and unbalanced conditional-sum adders</atitle><btitle>Proceedings of the IEEE SoutheastCon 2000. 'Preparing for The New Millennium' (Cat. No.00CH37105)</btitle><stitle>SECON</stitle><date>2000</date><risdate>2000</risdate><spage>359</spage><epage>364</epage><pages>359-364</pages><isbn>9780780363120</isbn><isbn>0780363124</isbn><abstract>In this paper the pair-fault (pf) model (Arjhan and Deshmukh 1998), its concept of multiple fault boundaries (MFBs) and fault-dominance are applied to detect multiple stuck-at faults of the conditional-sum type adders' carry-tree. There are 2n+1 test patterns (n is the operand width) to be applied through the primary inputs of the carry binary-trees. The tree can be balanced or unbalanced. For this purpose, the architecture of the adders is reformulated such that they will correspond to the parallel-prefix lookahead adders and the proof of testability is then followed.</abstract><pub>IEEE</pub><doi>10.1109/SECON.2000.845593</doi></addata></record>
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subjects Computer science
Delay
Electrical fault detection
Fault detection
Robustness
Testing
Upper bound
title Multiple-fault detection for the balanced and unbalanced conditional-sum adders
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T14%3A17%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Multiple-fault%20detection%20for%20the%20balanced%20and%20unbalanced%20conditional-sum%20adders&rft.btitle=Proceedings%20of%20the%20IEEE%20SoutheastCon%202000.%20'Preparing%20for%20The%20New%20Millennium'%20(Cat.%20No.00CH37105)&rft.au=Arjhan,%20C.&rft.date=2000&rft.spage=359&rft.epage=364&rft.pages=359-364&rft.isbn=9780780363120&rft.isbn_list=0780363124&rft_id=info:doi/10.1109/SECON.2000.845593&rft_dat=%3Cieee_6IE%3E845593%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=845593&rfr_iscdi=true