Enabling DIR (Designing-In-Reliability) through CAD capabilities
Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool exp...
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| creator | Potts, B. Hokinson, R. Kang, W. Riley, J. Doman, D. Cano, F. Durrant, N. |
| description | Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. CAD tool/data interface deals with core design tools that enable correct-by-construction such as reliability-constraint place-and-route tools. The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented. |
| doi_str_mv | 10.1109/ISQED.2000.838868 |
| format | Conference Proceeding |
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In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.</description><identifier>ISBN: 0769505252</identifier><identifier>ISBN: 9780769505251</identifier><identifier>DOI: 10.1109/ISQED.2000.838868</identifier><language>eng</language><publisher>IEEE</publisher><subject>Chip scale packaging ; Costs ; Design automation ; Design methodology ; Electrical capacitance tomography ; Electronic design automation and methodology ; Instruments ; Integrated circuit interconnections ; Risk analysis</subject><ispartof>Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. 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The DIR point solutions refer to reliability simulation or verification tools. Moreover, the high-level tool requirements on top five prioritized tool requirements are presented. In addition, the maturity matrix of DIR tool capabilities is presented in order to show both current and future DIR tool gaps. Also, a high-level roadmap of the team and future projects is presented.</description><subject>Chip scale packaging</subject><subject>Costs</subject><subject>Design automation</subject><subject>Design methodology</subject><subject>Electrical capacitance tomography</subject><subject>Electronic design automation and methodology</subject><subject>Instruments</subject><subject>Integrated circuit interconnections</subject><subject>Risk analysis</subject><isbn>0769505252</isbn><isbn>9780769505251</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0FLxDAUhAMiqOv-AD31qIfWl-SlSW4ubdXCgrjqeUmapBupdWnrYf-9hXoaZr5hYAi5oZBRCvqhfn-ryowBQKa4Urk6I1cgcy1AMMEuyHocv2YIiBxofkkeq97YLvZtUta75K70Y2z72aZ1n-58F42NXZxO98l0GH5-20NSbMqkMcclj368JufBdKNf_-uKfD5VH8VLun19rovNNm0p4pRqiwqVx1wEdME2QdmAzDZOBqdANsxJQCYkMG3cXNCOKoHgHQSusRF8RW6X3ei93x-H-G2G0375yP8A_dFG4w</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Potts, B.</creator><creator>Hokinson, R.</creator><creator>Kang, W.</creator><creator>Riley, J.</creator><creator>Doman, D.</creator><creator>Cano, F.</creator><creator>Durrant, N.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2000</creationdate><title>Enabling DIR (Designing-In-Reliability) through CAD capabilities</title><author>Potts, B. ; Hokinson, R. ; Kang, W. ; Riley, J. ; Doman, D. ; Cano, F. ; Durrant, N.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-g144t-9b4848e465f4dfbcf8bf42bcd7fd807c2d704257029addfb9d18540ed0f394c53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Chip scale packaging</topic><topic>Costs</topic><topic>Design automation</topic><topic>Design methodology</topic><topic>Electrical capacitance tomography</topic><topic>Electronic design automation and methodology</topic><topic>Instruments</topic><topic>Integrated circuit interconnections</topic><topic>Risk analysis</topic><toplevel>online_resources</toplevel><creatorcontrib>Potts, B.</creatorcontrib><creatorcontrib>Hokinson, R.</creatorcontrib><creatorcontrib>Kang, W.</creatorcontrib><creatorcontrib>Riley, J.</creatorcontrib><creatorcontrib>Doman, D.</creatorcontrib><creatorcontrib>Cano, F.</creatorcontrib><creatorcontrib>Durrant, N.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Potts, B.</au><au>Hokinson, R.</au><au>Kang, W.</au><au>Riley, J.</au><au>Doman, D.</au><au>Cano, F.</au><au>Durrant, N.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Enabling DIR (Designing-In-Reliability) through CAD capabilities</atitle><btitle>Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)</btitle><stitle>ISQED</stitle><date>2000</date><risdate>2000</risdate><spage>151</spage><epage>156</epage><pages>151-156</pages><isbn>0769505252</isbn><isbn>9780769505251</isbn><abstract>Chip designs are continuously getting larger and more complex. In response to these trends, design methodologies and tool requirements used in recent high-performance designs have been changing rapidly. A Design-In Reliability (DIR) Team was formed at SEMATECH and is composed of DIR and CAD tool experts from the member companies. The team's primary goals are to define and develop tool requirement needs of the members and to communicate those needs to the EDA industry, in turn fostering development of new and improved tools. In this paper, the DIR project goals and recommendations are presented along with prioritized tool needs or gaps. The tool gaps are put in two categories: CAD tool/data interface and DIR point solutions. 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| identifier | ISBN: 0769505252 |
| ispartof | Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), 2000, p.151-156 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chip scale packaging Costs Design automation Design methodology Electrical capacitance tomography Electronic design automation and methodology Instruments Integrated circuit interconnections Risk analysis |
| title | Enabling DIR (Designing-In-Reliability) through CAD capabilities |
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