Multitrack Power Factor Correction Architecture
Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the i...
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| Veröffentlicht in: | IEEE transactions on power electronics 2019-03, Vol.34 (3), p.2454-2466 |
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| container_title | IEEE transactions on power electronics |
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| creator | Chen, Minjie Chakraborty, Sombuddha Perreault, David J. |
| description | Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 \rm V_{\text{ac}}-265 \rm V_{\text{ac}}). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 \rm V_{\text{dc}} output, isolated multitrack PFC system with a power density of 50 W/in^3, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture. |
| doi_str_mv | 10.1109/TPEL.2018.2847284 |
| format | Article |
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This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>-265 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{dc}}</tex-math></inline-formula> output, isolated multitrack PFC system with a power density of 50 W/in<inline-formula><tex-math notation="LaTeX">^3</tex-math></inline-formula>, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.]]></description><identifier>ISSN: 0885-8993</identifier><identifier>EISSN: 1941-0107</identifier><identifier>DOI: 10.1109/TPEL.2018.2847284</identifier><identifier>CODEN: ITPEE8</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>AC–DC power conversion ; Architecture ; Capacitors ; Circuits ; Density measurement ; Domains ; Electric converters ; Electric potential ; Energy conversion efficiency ; grid-tied power electronics ; Inductors ; multitrack architecture ; Power converters ; Power efficiency ; Power factor ; power factor correction (PFC) ; Power system measurements ; Subsystems ; Switches ; Voltage control ; Zero voltage switching</subject><ispartof>IEEE transactions on power electronics, 2019-03, Vol.34 (3), p.2454-2466</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2019</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c336t-8155f60d085edb339554923302ccc6092feb52ba1cd5c0eefa41650b5303a20b3</citedby><cites>FETCH-LOGICAL-c336t-8155f60d085edb339554923302ccc6092feb52ba1cd5c0eefa41650b5303a20b3</cites><orcidid>0000-0003-0705-563X ; 0000-0002-0746-6191</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8385184$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8385184$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chen, Minjie</creatorcontrib><creatorcontrib>Chakraborty, Sombuddha</creatorcontrib><creatorcontrib>Perreault, David J.</creatorcontrib><title>Multitrack Power Factor Correction Architecture</title><title>IEEE transactions on power electronics</title><addtitle>TPEL</addtitle><description><![CDATA[Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>-265 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{dc}}</tex-math></inline-formula> output, isolated multitrack PFC system with a power density of 50 W/in<inline-formula><tex-math notation="LaTeX">^3</tex-math></inline-formula>, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.]]></description><subject>AC–DC power conversion</subject><subject>Architecture</subject><subject>Capacitors</subject><subject>Circuits</subject><subject>Density measurement</subject><subject>Domains</subject><subject>Electric converters</subject><subject>Electric potential</subject><subject>Energy conversion efficiency</subject><subject>grid-tied power electronics</subject><subject>Inductors</subject><subject>multitrack architecture</subject><subject>Power converters</subject><subject>Power efficiency</subject><subject>Power factor</subject><subject>power factor correction (PFC)</subject><subject>Power system measurements</subject><subject>Subsystems</subject><subject>Switches</subject><subject>Voltage control</subject><subject>Zero voltage switching</subject><issn>0885-8993</issn><issn>1941-0107</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kFFLwzAQx4MoOKcfQHwp-NzuLte0yeMYmwoT9zCfQ5ql2DmXmaaI396WDh-O47jf_w5-jN0jZIigZtvNcp1xQJlxmZd9XbAJqhxTQCgv2QSkFKlUiq7ZTdvuATAXgBM2e-0OsYnB2M9k439cSFbGRh-ShQ_B2dj4YzIP9qOJ_dAFd8uuanNo3d25T9n7arldPKfrt6eXxXydWqIiphKFqAvYgRRuVxEpIXLFiYBbawtQvHaV4JVBuxMWnKtNjoWAShCQ4VDRlD2Od0_Bf3eujXrvu3DsX2qOZUkoiHhP4UjZ4Ns2uFqfQvNlwq9G0IMXPXjRgxd99tJnHsZM45z75yVJgf32D9YeXTU</recordid><startdate>20190301</startdate><enddate>20190301</enddate><creator>Chen, Minjie</creator><creator>Chakraborty, Sombuddha</creator><creator>Perreault, David J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-0705-563X</orcidid><orcidid>https://orcid.org/0000-0002-0746-6191</orcidid></search><sort><creationdate>20190301</creationdate><title>Multitrack Power Factor Correction Architecture</title><author>Chen, Minjie ; Chakraborty, Sombuddha ; Perreault, David J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c336t-8155f60d085edb339554923302ccc6092feb52ba1cd5c0eefa41650b5303a20b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>AC–DC power conversion</topic><topic>Architecture</topic><topic>Capacitors</topic><topic>Circuits</topic><topic>Density measurement</topic><topic>Domains</topic><topic>Electric converters</topic><topic>Electric potential</topic><topic>Energy conversion efficiency</topic><topic>grid-tied power electronics</topic><topic>Inductors</topic><topic>multitrack architecture</topic><topic>Power converters</topic><topic>Power efficiency</topic><topic>Power factor</topic><topic>power factor correction (PFC)</topic><topic>Power system measurements</topic><topic>Subsystems</topic><topic>Switches</topic><topic>Voltage control</topic><topic>Zero voltage switching</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chen, Minjie</creatorcontrib><creatorcontrib>Chakraborty, Sombuddha</creatorcontrib><creatorcontrib>Perreault, David J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on power electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Minjie</au><au>Chakraborty, Sombuddha</au><au>Perreault, David J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Multitrack Power Factor Correction Architecture</atitle><jtitle>IEEE transactions on power electronics</jtitle><stitle>TPEL</stitle><date>2019-03-01</date><risdate>2019</risdate><volume>34</volume><issue>3</issue><spage>2454</spage><epage>2466</epage><pages>2454-2466</pages><issn>0885-8993</issn><eissn>1941-0107</eissn><coden>ITPEE8</coden><abstract><![CDATA[Single-phase universal-input ac-dc converters are needed in a wide range of applications. This paper presents a novel power factor correction (PFC) architecture that can achieve high-power density and high efficiency for grid-interface power electronics. The multitrack PFC architecture reduces the internal device voltage stress of the power converter subsystems, allowing PFC circuits to maintain zero-voltage-switching at high frequency (1 MHz-4 MHz) across universal input voltage range (85 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>-265 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{ac}}</tex-math></inline-formula>). The high performance of the power converter is enabled by delivering power in multiple stacked voltage domains and reconfiguring the power processing paths depending on the input voltage. This multitrack concept can be used together with many other design techniques for PFC systems to create mutual advantages in many function blocks. A prototype 150 W, universal ac input, 12 <inline-formula><tex-math notation="LaTeX">\rm V_{\text{dc}}</tex-math></inline-formula> output, isolated multitrack PFC system with a power density of 50 W/in<inline-formula><tex-math notation="LaTeX">^3</tex-math></inline-formula>, and a peak end-to-end efficiency of 92% has been built and tested to verify the effectiveness of the multitrack PFC architecture.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TPEL.2018.2847284</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0003-0705-563X</orcidid><orcidid>https://orcid.org/0000-0002-0746-6191</orcidid><oa>free_for_read</oa></addata></record> |
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| identifier | ISSN: 0885-8993 |
| ispartof | IEEE transactions on power electronics, 2019-03, Vol.34 (3), p.2454-2466 |
| issn | 0885-8993 1941-0107 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | AC–DC power conversion Architecture Capacitors Circuits Density measurement Domains Electric converters Electric potential Energy conversion efficiency grid-tied power electronics Inductors multitrack architecture Power converters Power efficiency Power factor power factor correction (PFC) Power system measurements Subsystems Switches Voltage control Zero voltage switching |
| title | Multitrack Power Factor Correction Architecture |
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