Computation of 2D 8×8 DCT Based on the Loeffler Factorization Using Algebraic Integer Encoding

This paper proposes a computational method for 2D 8×8 DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and it is shown to operate with exact computation-i.e., error-free arithmetic-up to the final reconstruction step (FRS). The proposed algebraic int...

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Veröffentlicht in:IEEE transactions on computers 2018-12, Vol.67 (12), p.1692-1702
Hauptverfasser: Coelho, Diego F. G., Nimmalapalli, Sushmabhargavi, Dimitrov, Vassil S., Madanayake, Arjuna, Cintra, Renato J., Tisserand, Arnaud
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Sprache:eng
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Zusammenfassung:This paper proposes a computational method for 2D 8×8 DCT based on algebraic integers. The proposed algorithm is based on the Loeffler 1D DCT algorithm, and it is shown to operate with exact computation-i.e., error-free arithmetic-up to the final reconstruction step (FRS). The proposed algebraic integer architecture maintains error-free computations until an entire block of DCT coefficients having size 8×8 is computed, unlike algorithms in the literature which claim to be error-free but in fact introduce arithmetic errors between the column- and row-wise 1D DCT stages in a 2D DCT operation. Fast algorithms are proposed for the final reconstruction step employing two approaches, namely, the expansion factor and dyadic approximation. A digital architecture is also proposed for a particular FRS algorithm, and is implemented on an FPGA platform for on-chip verification. The FPGA implementation operates at 360 MHz, and is capable of a real-time throughput of 3.6\cdot 10^8 2D DCTs of size 8×8 every second, with corresponding pixel rate of 2.3\cdot 10^{10} pixels per second. The digital architecture is synthesized using 180 nm CMOS standard cells and shows a chip area of 7.41 mm ^2 . The CMOS design is predicted to operate at 893 MHz clock frequency, at a dynamic power consumption 13.22 mW/MHz \cdot V _{sup}^2 .
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2018.2837755