Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology

A field-programmable multi-chip module containing one ORCA 3T/125 FPGA and 4 MByte DRAM was built using chip-on-chip technology. Module architecture and physical design issues are presented. A PCI board consisting of four chip-on-chip modules is also built as the test vehicle. The design environment...

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Hauptverfasser:	Wang, M.X., Suzuki, K., Dai, W.W.-M., Low, Y.L., O'Conner, K.J., Tai, K.L.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS logic circuits CMOS technology Computer architecture Costs Field programmable gate arrays Large scale integration Logic devices Packaging Random access memory Silicon
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creator	Wang, M.X. Suzuki, K. Dai, W.W.-M. Low, Y.L. O'Conner, K.J. Tai, K.L.
description	A field-programmable multi-chip module containing one ORCA 3T/125 FPGA and 4 MByte DRAM was built using chip-on-chip technology. Module architecture and physical design issues are presented. A PCI board consisting of four chip-on-chip modules is also built as the test vehicle. The design environment for this multi-chip module, including visual or C++ design entry and bit-serial datapath synthesis system, is also discussed. Some ongoing approaches, like double-flip technology and area I/O are also addressed.
doi_str_mv	10.1109/ASPDAC.2000.835097
format	Conference Proceeding
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	CMOS logic circuits CMOS technology Computer architecture Costs Field programmable gate arrays Large scale integration Logic devices Packaging Random access memory Silicon
title	Integration of large-scale FPGA and DRAM in a package using chip-on-chip technology
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