Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R_{\mathrm{\scriptscriptstyle ON}} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order di...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2018-04, Vol.65 (4), p.1157-1173
Hauptverfasser: Iizuka, Tetsuya, Ito, Takaaki, Abidi, Asad A.
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container_title IEEE transactions on circuits and systems. I, Regular papers
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Ito, Takaaki
Abidi, Asad A.
description Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R_{\mathrm{\scriptscriptstyle ON}} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and measurement results establish the accuracy of the analysis. Since the three sources of distortion each have a unique dependence on circuit parameters and the input signal frequency, a systematic method is shown to optimize an S/H circuit for least distortion.
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fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_8307227</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8307227</ieee_id><sourcerecordid>2013247647</sourcerecordid><originalsourceid>FETCH-LOGICAL-c359t-e45c7e7d2f61979b458b537df3e626ac5a16d146162e27ef3bf5a37d9fa3365a3</originalsourceid><addsrcrecordid>eNo9kMtqwzAQRUVpoWnaDyjdCLp2qof18DK4jwQCKSRdG8UeEQXHSiWnkL-v3ISu5sKcOwwHoUdKJpSS4mVdruYTRqieMFWoQqsrNKJC6IxoIq-HnBeZ5kzforsYd4SwgnA6QsvS7w8BttBF9wN42pn2FF3E3uJXF3sfeuc77DrcbwF_mvhHvb-t8crsDy1kpmuymW8bXLpQH11_j26saSM8XOYYfSW6nGWL5ce8nC6ymouizyAXtQLVMCtpeneTC70RXDWWg2TS1MJQ2dBcUsmAKbB8Y4VJ-8IazmWKY_R8vnsI_vsIsa92_hjS97FKFjjLlcxVouiZqoOPMYCtDsHtTThVlFSDt2rwNjR0dfGWOk_njgOAf15zohhT_BdIqWis</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2013247647</pqid></control><display><type>article</type><title>Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit</title><source>IEEE Xplore</source><creator>Iizuka, Tetsuya ; Ito, Takaaki ; Abidi, Asad A.</creator><creatorcontrib>Iizuka, Tetsuya ; Ito, Takaaki ; Abidi, Asad A.</creatorcontrib><description>Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R_{\mathrm{\scriptscriptstyle ON}} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and measurement results establish the accuracy of the analysis. Since the three sources of distortion each have a unique dependence on circuit parameters and the input signal frequency, a systematic method is shown to optimize an S/H circuit for least distortion.</description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2018.2797987</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Analytical models ; Charge injection ; Circuits ; Distortion ; Field effect transistor ; Field effect transistors ; harmonic distortion ; Integrated circuit modeling ; intermodulation distortion ; Logic gates ; Nonlinear distortion ; ON resistance ; sample-and-hold ; sampling ; sampling timing ; Switches</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2018-04, Vol.65 (4), p.1157-1173</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c359t-e45c7e7d2f61979b458b537df3e626ac5a16d146162e27ef3bf5a37d9fa3365a3</citedby><cites>FETCH-LOGICAL-c359t-e45c7e7d2f61979b458b537df3e626ac5a16d146162e27ef3bf5a37d9fa3365a3</cites><orcidid>0000-0002-7064-0738 ; 0000-0002-0822-0302 ; 0000-0002-1512-4714</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8307227$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8307227$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Iizuka, Tetsuya</creatorcontrib><creatorcontrib>Ito, Takaaki</creatorcontrib><creatorcontrib>Abidi, Asad A.</creatorcontrib><title>Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description>Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R_{\mathrm{\scriptscriptstyle ON}} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and measurement results establish the accuracy of the analysis. Since the three sources of distortion each have a unique dependence on circuit parameters and the input signal frequency, a systematic method is shown to optimize an S/H circuit for least distortion.</description><subject>Analytical models</subject><subject>Charge injection</subject><subject>Circuits</subject><subject>Distortion</subject><subject>Field effect transistor</subject><subject>Field effect transistors</subject><subject>harmonic distortion</subject><subject>Integrated circuit modeling</subject><subject>intermodulation distortion</subject><subject>Logic gates</subject><subject>Nonlinear distortion</subject><subject>ON resistance</subject><subject>sample-and-hold</subject><subject>sampling</subject><subject>sampling timing</subject><subject>Switches</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kMtqwzAQRUVpoWnaDyjdCLp2qof18DK4jwQCKSRdG8UeEQXHSiWnkL-v3ISu5sKcOwwHoUdKJpSS4mVdruYTRqieMFWoQqsrNKJC6IxoIq-HnBeZ5kzforsYd4SwgnA6QsvS7w8BttBF9wN42pn2FF3E3uJXF3sfeuc77DrcbwF_mvhHvb-t8crsDy1kpmuymW8bXLpQH11_j26saSM8XOYYfSW6nGWL5ce8nC6ymouizyAXtQLVMCtpeneTC70RXDWWg2TS1MJQ2dBcUsmAKbB8Y4VJ-8IazmWKY_R8vnsI_vsIsa92_hjS97FKFjjLlcxVouiZqoOPMYCtDsHtTThVlFSDt2rwNjR0dfGWOk_njgOAf15zohhT_BdIqWis</recordid><startdate>20180401</startdate><enddate>20180401</enddate><creator>Iizuka, Tetsuya</creator><creator>Ito, Takaaki</creator><creator>Abidi, Asad A.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-7064-0738</orcidid><orcidid>https://orcid.org/0000-0002-0822-0302</orcidid><orcidid>https://orcid.org/0000-0002-1512-4714</orcidid></search><sort><creationdate>20180401</creationdate><title>Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit</title><author>Iizuka, Tetsuya ; Ito, Takaaki ; Abidi, Asad A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c359t-e45c7e7d2f61979b458b537df3e626ac5a16d146162e27ef3bf5a37d9fa3365a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Analytical models</topic><topic>Charge injection</topic><topic>Circuits</topic><topic>Distortion</topic><topic>Field effect transistor</topic><topic>Field effect transistors</topic><topic>harmonic distortion</topic><topic>Integrated circuit modeling</topic><topic>intermodulation distortion</topic><topic>Logic gates</topic><topic>Nonlinear distortion</topic><topic>ON resistance</topic><topic>sample-and-hold</topic><topic>sampling</topic><topic>sampling timing</topic><topic>Switches</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Iizuka, Tetsuya</creatorcontrib><creatorcontrib>Ito, Takaaki</creatorcontrib><creatorcontrib>Abidi, Asad A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Xplore</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Iizuka, Tetsuya</au><au>Ito, Takaaki</au><au>Abidi, Asad A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2018-04-01</date><risdate>2018</risdate><volume>65</volume><issue>4</issue><spage>1157</spage><epage>1173</epage><pages>1157-1173</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract>Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) R_{\mathrm{\scriptscriptstyle ON}} -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and measurement results establish the accuracy of the analysis. Since the three sources of distortion each have a unique dependence on circuit parameters and the input signal frequency, a systematic method is shown to optimize an S/H circuit for least distortion.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2018.2797987</doi><tpages>17</tpages><orcidid>https://orcid.org/0000-0002-7064-0738</orcidid><orcidid>https://orcid.org/0000-0002-0822-0302</orcidid><orcidid>https://orcid.org/0000-0002-1512-4714</orcidid></addata></record>
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1558-0806
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source IEEE Xplore
subjects Analytical models
Charge injection
Circuits
Distortion
Field effect transistor
Field effect transistors
harmonic distortion
Integrated circuit modeling
intermodulation distortion
Logic gates
Nonlinear distortion
ON resistance
sample-and-hold
sampling
sampling timing
Switches
title Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T18%3A35%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Comprehensive%20Analysis%20of%20Distortion%20in%20the%20Passive%20FET%20Sample-and-Hold%20Circuit&rft.jtitle=IEEE%20transactions%20on%20circuits%20and%20systems.%20I,%20Regular%20papers&rft.au=Iizuka,%20Tetsuya&rft.date=2018-04-01&rft.volume=65&rft.issue=4&rft.spage=1157&rft.epage=1173&rft.pages=1157-1173&rft.issn=1549-8328&rft.eissn=1558-0806&rft.coden=ITCSCH&rft_id=info:doi/10.1109/TCSI.2018.2797987&rft_dat=%3Cproquest_RIE%3E2013247647%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2013247647&rft_id=info:pmid/&rft_ieee_id=8307227&rfr_iscdi=true