A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation
A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors inc...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2018-03, Vol.53 (3), p.884-895 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 53 |
| creator | Woo-Seok Choi Guanghua Shu Talegaonkar, Mrunmay Yubo Liu Da Wei Benini, Luca Hanumolu, Pavan Kumar |
| description | A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V. |
| doi_str_mv | 10.1109/JSSC.2017.2786716 |
| format | Article |
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Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2017.2786716</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Calibration ; Clocks ; CMOS ; Delays ; Electric potential ; Energy management ; Low-power I/O ; multi-phase calibration ; Multiplexing ; near-threshold-voltage circuit design ; near-threshold-voltage phase-locked loop (PLL) ; Offsets ; Phase locked loops ; Power management ; source-synchronous transceiver ; Threshold voltage ; Transceivers ; Transmitters</subject><ispartof>IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.884-895</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-ceabecc5b5d6c60f289cf328885130408111a7a82fdd61b9ffe794346c89fc203</citedby><cites>FETCH-LOGICAL-c293t-ceabecc5b5d6c60f289cf328885130408111a7a82fdd61b9ffe794346c89fc203</cites><orcidid>0000-0003-2559-6915 ; 0000-0001-7613-8995 ; 0000-0002-3556-8689 ; 0000-0001-7972-8616 ; 0000-0001-8068-3806</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8260536$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8260536$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Woo-Seok Choi</creatorcontrib><creatorcontrib>Guanghua Shu</creatorcontrib><creatorcontrib>Talegaonkar, Mrunmay</creatorcontrib><creatorcontrib>Yubo Liu</creatorcontrib><creatorcontrib>Da Wei</creatorcontrib><creatorcontrib>Benini, Luca</creatorcontrib><creatorcontrib>Hanumolu, Pavan Kumar</creatorcontrib><title>A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.</description><subject>Calibration</subject><subject>Clocks</subject><subject>CMOS</subject><subject>Delays</subject><subject>Electric potential</subject><subject>Energy management</subject><subject>Low-power I/O</subject><subject>multi-phase calibration</subject><subject>Multiplexing</subject><subject>near-threshold-voltage circuit design</subject><subject>near-threshold-voltage phase-locked loop (PLL)</subject><subject>Offsets</subject><subject>Phase locked loops</subject><subject>Power management</subject><subject>source-synchronous transceiver</subject><subject>Threshold voltage</subject><subject>Transceivers</subject><subject>Transmitters</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1OAjEUhRujiYg-gHHTxHWH3nbaaZeEKEqMLAaMu0mn08oQnMEWTHh7SyCubu7JOffnQ-geaAZA9WhWlpOMUSgyVihZgLxAAxBCESj45yUaUAqKaEbpNbqJcZ3aPFcwQPUY0ywXhGYF_sBAJJ7Wo5g0ppMmFN7ORjUu-32wjpSHzq5C3_X7iBfBdNG69tcFvIxt94XfnQlksQourvpNg-dbF8yu7btbdOXNJrq7cx2i5fPTYvJC3ubT18n4jVim-Y5YZ2pnrahFI62kniltPWdKKQGc5lQBgCmMYr5pJNTae1fonOfSKu0to3yIHk9zt6H_2bu4q9bp7C6trNLfBQPNhEwuOLls6GMMzlfb0H6bcKiAVkeU1RFldURZnVGmzMMp0zrn_v2KSSq45H9X1mtU</recordid><startdate>20180301</startdate><enddate>20180301</enddate><creator>Woo-Seok Choi</creator><creator>Guanghua Shu</creator><creator>Talegaonkar, Mrunmay</creator><creator>Yubo Liu</creator><creator>Da Wei</creator><creator>Benini, Luca</creator><creator>Hanumolu, Pavan Kumar</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. 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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.884-895 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_8260536 |
| source | IEEE Electronic Library (IEL) |
| subjects | Calibration Clocks CMOS Delays Electric potential Energy management Low-power I/O multi-phase calibration Multiplexing near-threshold-voltage circuit design near-threshold-voltage phase-locked loop (PLL) Offsets Phase locked loops Power management source-synchronous transceiver Threshold voltage Transceivers Transmitters |
| title | A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation |
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