FPGA implementation using Renoir tools: application for bit timing logic (BTL) synthesis of controller area network with 100% free error

Logic synthesis using VHDL simplifies considerably logic circuit design. However, when the application requires a few thousand lines of VHDL code, it is very beneficial to use graphic software that can produce the VHDL code. But, it is always necessary to master the VHDL language. In this paper we h...

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Bibliographische Detailangaben

Hauptverfasser:	Abouda, K., Ducaud, J., Henry, H., Aucouturier, J.L.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Circuit synthesis Field programmable gate arrays Graphics ISO Logic circuits Logic design Network synthesis Testing Timing
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