A 10-bit 300 MS/s 5.8 mW SAR ADC With Two-Stage Interpolation for PET Imaging

In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of sma...

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Veröffentlicht in:IEEE sensors journal 2018-03, Vol.18 (5), p.2006-2014
Hauptverfasser: Lei Qiu, Keping Wang, Kai Tang, Siek, Liter, Yuanjin Zheng
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container_end_page 2014
container_issue 5
container_start_page 2006
container_title IEEE sensors journal
container_volume 18
creator Lei Qiu
Keping Wang
Kai Tang
Siek, Liter
Yuanjin Zheng
description In this paper, a high speed low power 2b/cycle successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for medical imaging. The ADC adopts a two-stage differential pair based interpolation technique that can reduce resolution of the capacitive DAC and avoid usage of smaller unit capacitor. A meta-stability immunity technique is proposed to enhance the asynchronous conversion. A design example of 10-bit 2b/cycle SAR ADC with sampling rate up to 300 MS/s is fabricated. Dissipating 5.8 mW with 1.2 V supply and occupying an active area of 0.082 mm 2 , the measured SFDR and SNDR at Nyquist input are 59-dB and 51.5-dB respectively. It achieves an effective resolution bandwidth of 360 MHz and a figure-of-merit of 61fJ/conversion-step.
doi_str_mv 10.1109/JSEN.2018.2790581
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subjects 2b/cycle
Analog to digital conversion
Analog to digital converters
background offset calibration
Capacitors
Computer architecture
Digital imaging
Digital to analog converters
Immunity
Interpolation
Medical imaging
Positron emission
Positron emission tomography
SAR ADCs
Sensors
Switches
Tomography
title A 10-bit 300 MS/s 5.8 mW SAR ADC With Two-Stage Interpolation for PET Imaging
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