Gate oxide thinning effects at the edge of shallow trench isolation in the dual gate oxide process

We have investigated the degradation of thick gate oxide in the conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide operating under the bias of 1.8 and 2.5 V, respectively, on a single chip, a novel dual gate oxide process flow, without gate oxide...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Seok-Woo Lee, Ihl Hyun Cho, Sang Hyuk Park, Hong Goo Choi, Nam Gawk Kim, Jong-Kwan Kim, Sang Beom Han, KyungHo Lee
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS logic circuits Contamination Degradation Design for quality Oxidation Planarization Plasma temperature Resists Voltage Wet etching
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