Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis

Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, wh...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2018-09, Vol.37 (9), p.1802-1815
Hauptverfasser:	Liu, Junyi, Wickerson, John, Bayliss, Samuel, Constantinides, George A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Computer architecture Field-programmable gate array (FPGA) Hardware High level synthesis high-level synthesis (HLS) Iterative methods Level (quantity) loop pipelining Operation scheduling Optimization Pipeline processing Pipelines polyhedral model reconfigurable computing Runtime Source code Transformations
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