Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis

Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, wh...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 2018-09, Vol.37 (9), p.1802-1815
Hauptverfasser: Liu, Junyi, Wickerson, John, Bayliss, Samuel, Constantinides, George A.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 1815
container_issue 9
container_start_page 1802
container_title IEEE transactions on computer-aided design of integrated circuits and systems
container_volume 37
creator Liu, Junyi
Wickerson, John
Bayliss, Samuel
Constantinides, George A.
description Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7- 10{\times } faster, with a reasonable resource overhead.
doi_str_mv 10.1109/TCAD.2017.2783363
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_8207646</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8207646</ieee_id><sourcerecordid>2117132019</sourcerecordid><originalsourceid>FETCH-LOGICAL-c336t-d30269942da65405fc95f7d04a6abe7be8907d2caa07a0335dfba0bd0fbb2bc63</originalsourceid><addsrcrecordid>eNo9kF1LwzAUhoMoOKc_QLwpeJ15krTJcjk3dULBgfM6JE2yZXRtTTah_96OiVcHDs97Ph6E7glMCAH5tJ7PFhMKREyomDLG2QUaEckEzklBLtEIhjYGEHCNblLaAZC8oHKEZqu27rfORl3jZ52czRZ9o_ehysq27bJV6FwdmtBsMt_GbBk2W1y6H1dnn31z2LoU0i268rpO7u6vjtHX68t6vsTlx9v7fFbiajjngC0DyqXMqdW8yKHwlSy8sJBrro0Txk0lCEsrrUFoYKyw3mgwFrwx1FScjdHjeW4X2--jSwe1a4-xGVYqSoggbPheDhQ5U1VsU4rOqy6GvY69IqBOptTJlDqZUn-mhszDOROcc__8lILgOWe_1WFkIQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2117132019</pqid></control><display><type>article</type><title>Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis</title><source>IEEE Electronic Library (IEL)</source><creator>Liu, Junyi ; Wickerson, John ; Bayliss, Samuel ; Constantinides, George A.</creator><creatorcontrib>Liu, Junyi ; Wickerson, John ; Bayliss, Samuel ; Constantinides, George A.</creatorcontrib><description>Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;10{\times } &lt;/tex-math&gt;&lt;/inline-formula&gt; faster, with a reasonable resource overhead.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.2017.2783363</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Clocks ; Computer architecture ; Field-programmable gate array (FPGA) ; Hardware ; High level synthesis ; high-level synthesis (HLS) ; Iterative methods ; Level (quantity) ; loop pipelining ; Operation scheduling ; Optimization ; Pipeline processing ; Pipelines ; polyhedral model ; reconfigurable computing ; Runtime ; Source code ; Transformations</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 2018-09, Vol.37 (9), p.1802-1815</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c336t-d30269942da65405fc95f7d04a6abe7be8907d2caa07a0335dfba0bd0fbb2bc63</citedby><cites>FETCH-LOGICAL-c336t-d30269942da65405fc95f7d04a6abe7be8907d2caa07a0335dfba0bd0fbb2bc63</cites><orcidid>0000-0002-4277-1802 ; 0000-0001-6735-5533</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8207646$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8207646$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Liu, Junyi</creatorcontrib><creatorcontrib>Wickerson, John</creatorcontrib><creatorcontrib>Bayliss, Samuel</creatorcontrib><creatorcontrib>Constantinides, George A.</creatorcontrib><title>Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;10{\times } &lt;/tex-math&gt;&lt;/inline-formula&gt; faster, with a reasonable resource overhead.</description><subject>Clocks</subject><subject>Computer architecture</subject><subject>Field-programmable gate array (FPGA)</subject><subject>Hardware</subject><subject>High level synthesis</subject><subject>high-level synthesis (HLS)</subject><subject>Iterative methods</subject><subject>Level (quantity)</subject><subject>loop pipelining</subject><subject>Operation scheduling</subject><subject>Optimization</subject><subject>Pipeline processing</subject><subject>Pipelines</subject><subject>polyhedral model</subject><subject>reconfigurable computing</subject><subject>Runtime</subject><subject>Source code</subject><subject>Transformations</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2018</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kF1LwzAUhoMoOKc_QLwpeJ15krTJcjk3dULBgfM6JE2yZXRtTTah_96OiVcHDs97Ph6E7glMCAH5tJ7PFhMKREyomDLG2QUaEckEzklBLtEIhjYGEHCNblLaAZC8oHKEZqu27rfORl3jZ52czRZ9o_ehysq27bJV6FwdmtBsMt_GbBk2W1y6H1dnn31z2LoU0i268rpO7u6vjtHX68t6vsTlx9v7fFbiajjngC0DyqXMqdW8yKHwlSy8sJBrro0Txk0lCEsrrUFoYKyw3mgwFrwx1FScjdHjeW4X2--jSwe1a4-xGVYqSoggbPheDhQ5U1VsU4rOqy6GvY69IqBOptTJlDqZUn-mhszDOROcc__8lILgOWe_1WFkIQ</recordid><startdate>20180901</startdate><enddate>20180901</enddate><creator>Liu, Junyi</creator><creator>Wickerson, John</creator><creator>Bayliss, Samuel</creator><creator>Constantinides, George A.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><orcidid>https://orcid.org/0000-0002-4277-1802</orcidid><orcidid>https://orcid.org/0000-0001-6735-5533</orcidid></search><sort><creationdate>20180901</creationdate><title>Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis</title><author>Liu, Junyi ; Wickerson, John ; Bayliss, Samuel ; Constantinides, George A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c336t-d30269942da65405fc95f7d04a6abe7be8907d2caa07a0335dfba0bd0fbb2bc63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2018</creationdate><topic>Clocks</topic><topic>Computer architecture</topic><topic>Field-programmable gate array (FPGA)</topic><topic>Hardware</topic><topic>High level synthesis</topic><topic>high-level synthesis (HLS)</topic><topic>Iterative methods</topic><topic>Level (quantity)</topic><topic>loop pipelining</topic><topic>Operation scheduling</topic><topic>Optimization</topic><topic>Pipeline processing</topic><topic>Pipelines</topic><topic>polyhedral model</topic><topic>reconfigurable computing</topic><topic>Runtime</topic><topic>Source code</topic><topic>Transformations</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Liu, Junyi</creatorcontrib><creatorcontrib>Wickerson, John</creatorcontrib><creatorcontrib>Bayliss, Samuel</creatorcontrib><creatorcontrib>Constantinides, George A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Junyi</au><au>Wickerson, John</au><au>Bayliss, Samuel</au><au>Constantinides, George A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2018-09-01</date><risdate>2018</risdate><volume>37</volume><issue>9</issue><spage>1802</spage><epage>1815</epage><pages>1802-1815</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation scheduling and parallel memory accesses. Nonetheless, when loops contain complex memory dependencies, current techniques cannot generate high performance pipelines. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain dependencies (i.e., parameterized by an undetermined variable) and/or nonuniform dependencies (i.e., varying between loop iterations). Our optimization allows a pipeline to be statically scheduled without the aforementioned memory dependencies, but an associated controller will change the execution speed of loop iterations at runtime. This allows the augmented pipeline to process each loop iteration as fast as possible without violating memory dependencies. We use a parametric polyhedral analysis to generate the control logic for when to safely run all loop iterations in the pipeline and when to break the pipeline execution to resolve memory conflicts. Our techniques have been prototyped in an automated source-to-source code transformation framework, with Xilinx Vivado HLS, a leading HLS tool, as the RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement optimized pipelines at almost the same clock speed as without our transformations, running approximately 3.7-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;10{\times } &lt;/tex-math&gt;&lt;/inline-formula&gt; faster, with a reasonable resource overhead.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCAD.2017.2783363</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0002-4277-1802</orcidid><orcidid>https://orcid.org/0000-0001-6735-5533</orcidid><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0278-0070
ispartof IEEE transactions on computer-aided design of integrated circuits and systems, 2018-09, Vol.37 (9), p.1802-1815
issn 0278-0070
1937-4151
language eng
recordid cdi_ieee_primary_8207646
source IEEE Electronic Library (IEL)
subjects Clocks
Computer architecture
Field-programmable gate array (FPGA)
Hardware
High level synthesis
high-level synthesis (HLS)
Iterative methods
Level (quantity)
loop pipelining
Operation scheduling
Optimization
Pipeline processing
Pipelines
polyhedral model
reconfigurable computing
Runtime
Source code
Transformations
title Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-02T05%3A04%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Polyhedral-Based%20Dynamic%20Loop%20Pipelining%20for%20High-Level%20Synthesis&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Liu,%20Junyi&rft.date=2018-09-01&rft.volume=37&rft.issue=9&rft.spage=1802&rft.epage=1815&rft.pages=1802-1815&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/TCAD.2017.2783363&rft_dat=%3Cproquest_RIE%3E2117132019%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2117132019&rft_id=info:pmid/&rft_ieee_id=8207646&rfr_iscdi=true