Assessing Layout Density Benefits of Vertical Channel Devices

Vertical channel devices have been considered as promising candidates for sub-5 nm regime for the reduced area and large driving current. Several styles of layout designs and fabrication details of vertical channel devices have been proposed. However, due to the fast-changing manufacturing constrain...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2018-12, Vol.37 (12), p.3211-3215
Hauptverfasser:	Wang, Wei-Che, Zhao, Charles, Gupta, Puneet
Format:	Artikel
Sprache:	eng
Schlagworte:	Design rules Devices FinFETs Inertia Layout layout optimization Layouts Manufacturing processes Pins technology assessment vertical channel device
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!