A transistor level placement tool for custom cell generation
In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obt...
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| creator | Dash, R.K. Pramod, T. Vasudevan, V. Ramakrishna, M. |
| description | In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method. |
| doi_str_mv | 10.1109/ICVD.2000.812617 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_812617</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>812617</ieee_id><sourcerecordid>812617</sourcerecordid><originalsourceid>FETCH-ieee_primary_8126173</originalsourceid><addsrcrecordid>eNp9zjsLwjAUhuGDF7BVd3HKH2g9aW3SgotURXdxLaGcSiW9kETBf29BZ6dvePjgBVhxDDnHbHPJb4cwQsQw5ZHgcgReFKcYiCyKx-CjFFmC21SKCXgcRRxkQsgZ-NY-hlOaoPRgt2fOqNbW1nWGaXqRZr1WJTXUOua6TrNqgPI5eMNK0prdqSWjXN21C5hWSlta_nYO69Pxmp-DmoiK3tSNMu_iGxf_xQ_RBToY</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A transistor level placement tool for custom cell generation</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Dash, R.K. ; Pramod, T. ; Vasudevan, V. ; Ramakrishna, M.</creator><creatorcontrib>Dash, R.K. ; Pramod, T. ; Vasudevan, V. ; Ramakrishna, M.</creatorcontrib><description>In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 0769504876</identifier><identifier>ISBN: 9780769504872</identifier><identifier>EISSN: 2380-6923</identifier><identifier>DOI: 10.1109/ICVD.2000.812617</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; CMOS logic circuits ; CMOS technology ; Costs ; Libraries ; Parasitic capacitance ; Programmable logic arrays ; Simulated annealing ; Transistors ; Very large scale integration</subject><ispartof>VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design, 2000, p.254-257</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/812617$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/812617$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Dash, R.K.</creatorcontrib><creatorcontrib>Pramod, T.</creatorcontrib><creatorcontrib>Vasudevan, V.</creatorcontrib><creatorcontrib>Ramakrishna, M.</creatorcontrib><title>A transistor level placement tool for custom cell generation</title><title>VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design</title><addtitle>ICVD</addtitle><description>In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method.</description><subject>Circuit simulation</subject><subject>CMOS logic circuits</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>Libraries</subject><subject>Parasitic capacitance</subject><subject>Programmable logic arrays</subject><subject>Simulated annealing</subject><subject>Transistors</subject><subject>Very large scale integration</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>0769504876</isbn><isbn>9780769504872</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2000</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9zjsLwjAUhuGDF7BVd3HKH2g9aW3SgotURXdxLaGcSiW9kETBf29BZ6dvePjgBVhxDDnHbHPJb4cwQsQw5ZHgcgReFKcYiCyKx-CjFFmC21SKCXgcRRxkQsgZ-NY-hlOaoPRgt2fOqNbW1nWGaXqRZr1WJTXUOua6TrNqgPI5eMNK0prdqSWjXN21C5hWSlta_nYO69Pxmp-DmoiK3tSNMu_iGxf_xQ_RBToY</recordid><startdate>2000</startdate><enddate>2000</enddate><creator>Dash, R.K.</creator><creator>Pramod, T.</creator><creator>Vasudevan, V.</creator><creator>Ramakrishna, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>2000</creationdate><title>A transistor level placement tool for custom cell generation</title><author>Dash, R.K. ; Pramod, T. ; Vasudevan, V. ; Ramakrishna, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_8126173</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2000</creationdate><topic>Circuit simulation</topic><topic>CMOS logic circuits</topic><topic>CMOS technology</topic><topic>Costs</topic><topic>Libraries</topic><topic>Parasitic capacitance</topic><topic>Programmable logic arrays</topic><topic>Simulated annealing</topic><topic>Transistors</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Dash, R.K.</creatorcontrib><creatorcontrib>Pramod, T.</creatorcontrib><creatorcontrib>Vasudevan, V.</creatorcontrib><creatorcontrib>Ramakrishna, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Dash, R.K.</au><au>Pramod, T.</au><au>Vasudevan, V.</au><au>Ramakrishna, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A transistor level placement tool for custom cell generation</atitle><btitle>VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design</btitle><stitle>ICVD</stitle><date>2000</date><risdate>2000</risdate><spage>254</spage><epage>257</epage><pages>254-257</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>0769504876</isbn><isbn>9780769504872</isbn><abstract>In this paper, we present a transistor level placer suitable for the macro cell design style. The Eulerian path finding algorithm is used to create locally optimal placements of groups of transistors, called stacks. Typically however there are large disparities in the sizes of the various stacks obtained. It is therefore not always possible to meet the desired cell aspect ratio/height/width specifications. In our placer, these stacks can be reshaped so that the constraints on the cell are met. The optimisation tool used is simulated annealing. Placements for cells containing several hundred transistors were generated using this method.</abstract><pub>IEEE</pub><doi>10.1109/ICVD.2000.812617</doi></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation CMOS logic circuits CMOS technology Costs Libraries Parasitic capacitance Programmable logic arrays Simulated annealing Transistors Very large scale integration |
| title | A transistor level placement tool for custom cell generation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T15%3A22%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20transistor%20level%20placement%20tool%20for%20custom%20cell%20generation&rft.btitle=VLSI%20Design%202000.%20Wireless%20and%20Digital%20Imaging%20in%20the%20Millennium.%20Proceedings%20of%2013th%20International%20Conference%20on%20VLSI%20Design&rft.au=Dash,%20R.K.&rft.date=2000&rft.spage=254&rft.epage=257&rft.pages=254-257&rft.issn=1063-9667&rft.eissn=2380-6923&rft.isbn=0769504876&rft.isbn_list=9780769504872&rft_id=info:doi/10.1109/ICVD.2000.812617&rft_dat=%3Cieee_6IE%3E812617%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=812617&rfr_iscdi=true |