An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems
This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-i...
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| container_end_page | 96 vol.1 |
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| container_start_page | 93 |
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| creator | Doumenis, G. Konstantoulakis, G. Korinthios, G. Lykakis, G. Reisis, D. Synnefakis, G. |
| description | This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true "system on a chip" solution. |
| doi_str_mv | 10.1109/ICECS.1999.812231 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_812231</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>812231</ieee_id><sourcerecordid>812231</sourcerecordid><originalsourceid>FETCH-ieee_primary_8122313</originalsourceid><addsrcrecordid>eNp9zjFvwjAUBGBLqBJQ8gNgeiMdEuxECfEYRaAywADskQnPyCi2I9sM_HugdOaWO-lbjpApowljlC829ao-JIxznpQsTTM2IGO6LGmWF2XKhyTy_kqfyfMyLYoRkZUBlFK1Ck2A1uremteab3bxvtr-gLQOTjcp0YEWRlxQv1iYM-hbF1TcOxtsaztQuu_-UARlDSgD1XEL_u4Daj8hX1J0HqP__iaz9epY_8YKEZveKS3cvXk_zj7iAzo_Rcc</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Doumenis, G. ; Konstantoulakis, G. ; Korinthios, G. ; Lykakis, G. ; Reisis, D. ; Synnefakis, G.</creator><creatorcontrib>Doumenis, G. ; Konstantoulakis, G. ; Korinthios, G. ; Lykakis, G. ; Reisis, D. ; Synnefakis, G.</creatorcontrib><description>This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true "system on a chip" solution.</description><identifier>ISBN: 0780356829</identifier><identifier>ISBN: 9780780356825</identifier><identifier>DOI: 10.1109/ICECS.1999.812231</identifier><language>eng</language><publisher>IEEE</publisher><subject>Communication system control ; Cost function ; Design optimization ; Intelligent networks ; Memory management ; Physics ; Random access memory ; Scheduling ; System performance ; Very large scale integration</subject><ispartof>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, Vol.1, p.93-96 vol.1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/812231$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/812231$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Doumenis, G.</creatorcontrib><creatorcontrib>Konstantoulakis, G.</creatorcontrib><creatorcontrib>Korinthios, G.</creatorcontrib><creatorcontrib>Lykakis, G.</creatorcontrib><creatorcontrib>Reisis, D.</creatorcontrib><creatorcontrib>Synnefakis, G.</creatorcontrib><title>An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems</title><title>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)</title><addtitle>ICECS</addtitle><description>This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true "system on a chip" solution.</description><subject>Communication system control</subject><subject>Cost function</subject><subject>Design optimization</subject><subject>Intelligent networks</subject><subject>Memory management</subject><subject>Physics</subject><subject>Random access memory</subject><subject>Scheduling</subject><subject>System performance</subject><subject>Very large scale integration</subject><isbn>0780356829</isbn><isbn>9780780356825</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9zjFvwjAUBGBLqBJQ8gNgeiMdEuxECfEYRaAywADskQnPyCi2I9sM_HugdOaWO-lbjpApowljlC829ao-JIxznpQsTTM2IGO6LGmWF2XKhyTy_kqfyfMyLYoRkZUBlFK1Ck2A1uremteab3bxvtr-gLQOTjcp0YEWRlxQv1iYM-hbF1TcOxtsaztQuu_-UARlDSgD1XEL_u4Daj8hX1J0HqP__iaz9epY_8YKEZveKS3cvXk_zj7iAzo_Rcc</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Doumenis, G.</creator><creator>Konstantoulakis, G.</creator><creator>Korinthios, G.</creator><creator>Lykakis, G.</creator><creator>Reisis, D.</creator><creator>Synnefakis, G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1999</creationdate><title>An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems</title><author>Doumenis, G. ; Konstantoulakis, G. ; Korinthios, G. ; Lykakis, G. ; Reisis, D. ; Synnefakis, G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_8122313</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Communication system control</topic><topic>Cost function</topic><topic>Design optimization</topic><topic>Intelligent networks</topic><topic>Memory management</topic><topic>Physics</topic><topic>Random access memory</topic><topic>Scheduling</topic><topic>System performance</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Doumenis, G.</creatorcontrib><creatorcontrib>Konstantoulakis, G.</creatorcontrib><creatorcontrib>Korinthios, G.</creatorcontrib><creatorcontrib>Lykakis, G.</creatorcontrib><creatorcontrib>Reisis, D.</creatorcontrib><creatorcontrib>Synnefakis, G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Doumenis, G.</au><au>Konstantoulakis, G.</au><au>Korinthios, G.</au><au>Lykakis, G.</au><au>Reisis, D.</au><au>Synnefakis, G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems</atitle><btitle>ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)</btitle><stitle>ICECS</stitle><date>1999</date><risdate>1999</risdate><volume>1</volume><spage>93</spage><epage>96 vol.1</epage><pages>93-96 vol.1</pages><isbn>0780356829</isbn><isbn>9780780356825</isbn><abstract>This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true "system on a chip" solution.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.1999.812231</doi></addata></record> |
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| identifier | ISBN: 0780356829 |
| ispartof | ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, Vol.1, p.93-96 vol.1 |
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| language | eng |
| recordid | cdi_ieee_primary_812231 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Communication system control Cost function Design optimization Intelligent networks Memory management Physics Random access memory Scheduling System performance Very large scale integration |
| title | An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T12%3A29%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20efficient%20component%20(IN-RAM)%20for%20buffer%20management%20and%20multi-protocol%20implementation%20in%20ATM%20systems&rft.btitle=ICECS'99.%20Proceedings%20of%20ICECS%20'99.%206th%20IEEE%20International%20Conference%20on%20Electronics,%20Circuits%20and%20Systems%20(Cat.%20No.99EX357)&rft.au=Doumenis,%20G.&rft.date=1999&rft.volume=1&rft.spage=93&rft.epage=96%20vol.1&rft.pages=93-96%20vol.1&rft.isbn=0780356829&rft.isbn_list=9780780356825&rft_id=info:doi/10.1109/ICECS.1999.812231&rft_dat=%3Cieee_6IE%3E812231%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=812231&rfr_iscdi=true |