An architectural survey and modeling of data cache memories in Verilog HDL
In this paper two data cache architectures-a direct-mapped write-through data cache and a direct-mapped, write-through, write buffering data cache-are presented followed by a synthesized implementation of these data cache models. Strategies for testing, results of simulations with Verilog-XL/sup TM/...
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creator | Crisu, D. |
description | In this paper two data cache architectures-a direct-mapped write-through data cache and a direct-mapped, write-through, write buffering data cache-are presented followed by a synthesized implementation of these data cache models. Strategies for testing, results of simulations with Verilog-XL/sup TM/ and methods of architectural improvement are also given. |
doi_str_mv | 10.1109/SMICND.1999.810448 |
format | Conference Proceeding |
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subjects | Hardware design languages Hazards Laboratories Pipelines Random access memory Read-write memory Reduced instruction set computing Signal processing System buses Testing |
title | An architectural survey and modeling of data cache memories in Verilog HDL |
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