Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration
A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 2017-12, Vol.64 (12), p.5065-5072 |
|---|---|
| Hauptverfasser: | , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 5072 |
|---|---|
| container_issue | 12 |
| container_start_page | 5065 |
| container_title | IEEE transactions on electron devices |
| container_volume | 64 |
| creator | Hashiguchi, Hideto Fukushima, Takafumi Hashimoto, Hiroyuki Ji-Cheol Bea Murugesan, Mariappan Kino, Hisashi Tanaka, Tetsu Koyanagi, Mitsumasa |
| description | A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion. |
| doi_str_mv | 10.1109/TED.2017.2767598 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_8101564</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>8101564</ieee_id><sourcerecordid>10_1109_TED_2017_2767598</sourcerecordid><originalsourceid>FETCH-LOGICAL-c329t-abaf07c9b5f1e1b059f1ed1669bfa3e9d15922863013c70e22cf69f6cb2f29a63</originalsourceid><addsrcrecordid>eNo9kE1OwzAQRi0EEqWwR2LjC7j4J3HiZUlbqFSJRdOyjBxn3AbSpLK96RG4NS5UrEYz872R5iH0yOiEMaqey_lswinLJjyTWaryKzRiaZoRJRN5jUaUspwokYtbdOf9Z2xlkvAR-l5DZ8nUezjU3QnrvsHzDkxwgw86tAYX2rkWHC7B7PuhG3YnbAeHt60mK-0DLtdbvBjcIYaHHm982-9w6XTvbYTWQZuvOCEv2kODi317JGEgH_q8FGSGl32Anftl79GN1Z2Hh0sdo81iXhZvZPX-uiymK2IEV4HoWluaGVWnlgGraapibZiUqrZagGpYqjjPpaBMmIwC58ZKZaWpueVKSzFG9O-uiT96B7Y6uvag3alitDqrrKLK6qyyuqiMyNMf0gLAfzxnlKUyET93i3FQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration</title><source>IEEE Electronic Library (IEL)</source><creator>Hashiguchi, Hideto ; Fukushima, Takafumi ; Hashimoto, Hiroyuki ; Ji-Cheol Bea ; Murugesan, Mariappan ; Kino, Hisashi ; Tanaka, Tetsu ; Koyanagi, Mitsumasa</creator><creatorcontrib>Hashiguchi, Hideto ; Fukushima, Takafumi ; Hashimoto, Hiroyuki ; Ji-Cheol Bea ; Murugesan, Mariappan ; Kino, Hisashi ; Tanaka, Tetsu ; Koyanagi, Mitsumasa</creatorcontrib><description>A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2017.2767598</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capillary self-assembly ; chip-to-wafer 3-D integration ; electrostatic adhesion ; Electrostatics ; Reliability engineering ; Self-assembly ; Surface discharges ; Surface treatment ; temporary bonding/debonding ; transfer stacking ; Wafer scale integration</subject><ispartof>IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5065-5072</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c329t-abaf07c9b5f1e1b059f1ed1669bfa3e9d15922863013c70e22cf69f6cb2f29a63</citedby><cites>FETCH-LOGICAL-c329t-abaf07c9b5f1e1b059f1ed1669bfa3e9d15922863013c70e22cf69f6cb2f29a63</cites><orcidid>0000-0003-2303-8178 ; 0000-0002-5805-9000 ; 0000-0003-4726-4217</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8101564$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8101564$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hashiguchi, Hideto</creatorcontrib><creatorcontrib>Fukushima, Takafumi</creatorcontrib><creatorcontrib>Hashimoto, Hiroyuki</creatorcontrib><creatorcontrib>Ji-Cheol Bea</creatorcontrib><creatorcontrib>Murugesan, Mariappan</creatorcontrib><creatorcontrib>Kino, Hisashi</creatorcontrib><creatorcontrib>Tanaka, Tetsu</creatorcontrib><creatorcontrib>Koyanagi, Mitsumasa</creatorcontrib><title>Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.</description><subject>Capillary self-assembly</subject><subject>chip-to-wafer 3-D integration</subject><subject>electrostatic adhesion</subject><subject>Electrostatics</subject><subject>Reliability engineering</subject><subject>Self-assembly</subject><subject>Surface discharges</subject><subject>Surface treatment</subject><subject>temporary bonding/debonding</subject><subject>transfer stacking</subject><subject>Wafer scale integration</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1OwzAQRi0EEqWwR2LjC7j4J3HiZUlbqFSJRdOyjBxn3AbSpLK96RG4NS5UrEYz872R5iH0yOiEMaqey_lswinLJjyTWaryKzRiaZoRJRN5jUaUspwokYtbdOf9Z2xlkvAR-l5DZ8nUezjU3QnrvsHzDkxwgw86tAYX2rkWHC7B7PuhG3YnbAeHt60mK-0DLtdbvBjcIYaHHm982-9w6XTvbYTWQZuvOCEv2kODi317JGEgH_q8FGSGl32Anftl79GN1Z2Hh0sdo81iXhZvZPX-uiymK2IEV4HoWluaGVWnlgGraapibZiUqrZagGpYqjjPpaBMmIwC58ZKZaWpueVKSzFG9O-uiT96B7Y6uvag3alitDqrrKLK6qyyuqiMyNMf0gLAfzxnlKUyET93i3FQ</recordid><startdate>201712</startdate><enddate>201712</enddate><creator>Hashiguchi, Hideto</creator><creator>Fukushima, Takafumi</creator><creator>Hashimoto, Hiroyuki</creator><creator>Ji-Cheol Bea</creator><creator>Murugesan, Mariappan</creator><creator>Kino, Hisashi</creator><creator>Tanaka, Tetsu</creator><creator>Koyanagi, Mitsumasa</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0003-2303-8178</orcidid><orcidid>https://orcid.org/0000-0002-5805-9000</orcidid><orcidid>https://orcid.org/0000-0003-4726-4217</orcidid></search><sort><creationdate>201712</creationdate><title>Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration</title><author>Hashiguchi, Hideto ; Fukushima, Takafumi ; Hashimoto, Hiroyuki ; Ji-Cheol Bea ; Murugesan, Mariappan ; Kino, Hisashi ; Tanaka, Tetsu ; Koyanagi, Mitsumasa</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c329t-abaf07c9b5f1e1b059f1ed1669bfa3e9d15922863013c70e22cf69f6cb2f29a63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Capillary self-assembly</topic><topic>chip-to-wafer 3-D integration</topic><topic>electrostatic adhesion</topic><topic>Electrostatics</topic><topic>Reliability engineering</topic><topic>Self-assembly</topic><topic>Surface discharges</topic><topic>Surface treatment</topic><topic>temporary bonding/debonding</topic><topic>transfer stacking</topic><topic>Wafer scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hashiguchi, Hideto</creatorcontrib><creatorcontrib>Fukushima, Takafumi</creatorcontrib><creatorcontrib>Hashimoto, Hiroyuki</creatorcontrib><creatorcontrib>Ji-Cheol Bea</creatorcontrib><creatorcontrib>Murugesan, Mariappan</creatorcontrib><creatorcontrib>Kino, Hisashi</creatorcontrib><creatorcontrib>Tanaka, Tetsu</creatorcontrib><creatorcontrib>Koyanagi, Mitsumasa</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hashiguchi, Hideto</au><au>Fukushima, Takafumi</au><au>Hashimoto, Hiroyuki</au><au>Ji-Cheol Bea</au><au>Murugesan, Mariappan</au><au>Kino, Hisashi</au><au>Tanaka, Tetsu</au><au>Koyanagi, Mitsumasa</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2017-12</date><risdate>2017</risdate><volume>64</volume><issue>12</issue><spage>5065</spage><epage>5072</epage><pages>5065-5072</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.</abstract><pub>IEEE</pub><doi>10.1109/TED.2017.2767598</doi><tpages>8</tpages><orcidid>https://orcid.org/0000-0003-2303-8178</orcidid><orcidid>https://orcid.org/0000-0002-5805-9000</orcidid><orcidid>https://orcid.org/0000-0003-4726-4217</orcidid></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 2017-12, Vol.64 (12), p.5065-5072 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_ieee_primary_8101564 |
| source | IEEE Electronic Library (IEL) |
| subjects | Capillary self-assembly chip-to-wafer 3-D integration electrostatic adhesion Electrostatics Reliability engineering Self-assembly Surface discharges Surface treatment temporary bonding/debonding transfer stacking Wafer scale integration |
| title | Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T08%3A29%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Self-Assembly%20and%20Electrostatic%20Carrier%20Technology%20for%20Via-Last%20TSV%20Formation%20Using%20Transfer%20Stacking-Based%20Chip-to-Wafer%203-D%20Integration&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Hashiguchi,%20Hideto&rft.date=2017-12&rft.volume=64&rft.issue=12&rft.spage=5065&rft.epage=5072&rft.pages=5065-5072&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2017.2767598&rft_dat=%3Ccrossref_RIE%3E10_1109_TED_2017_2767598%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=8101564&rfr_iscdi=true |