Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting i...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2018-02, Vol.26 (2), p.404-415
Hauptverfasser:	O'Hare, Daniel, Scanlan, Anthony G., Thompson, Eric, Mullane, Brendan
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog-to-digital conversion antialias filter Bandwidth Capacitors Clocks CMOS analog integrated circuits continuous time (CT) Delays Estimation pipeline Pipelines Switches
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