Low overhead test point insertion for scan-based BIST

This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorith...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Nakao, M., Kobayashi, S., Hatayama, K., Iijima, K., Terada, S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Added delay Built-in self-test Circuit faults Circuit testing Delay effects Flip-flops Laboratories Large scale integration Pins Timing
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