Low overhead test point insertion for scan-based BIST
This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorith...
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| creator | Nakao, M. Kobayashi, S. Hatayama, K. Iijima, K. Terada, S. |
| description | This paper presents a practical test point insertion method for scan-based BIST. To apply test point insertion in actual LSIs, especially high performance LSIs, it is important to reduce the delay penalty and the area overhead of the inserted test points. Here efficient test point selection algorithms, which are suitable for utilizing overhead reduction approaches such as restricted cell replacement, test point flip-flops sharing, are proposed to meet the above requirements. The effectiveness of the algorithms is demonstrated by some experiments. |
| doi_str_mv | 10.1109/TEST.1999.805649 |
| format | Conference Proceeding |
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The effectiveness of the algorithms is demonstrated by some experiments.</description><subject>Added delay</subject><subject>Built-in self-test</subject><subject>Circuit faults</subject><subject>Circuit testing</subject><subject>Delay effects</subject><subject>Flip-flops</subject><subject>Laboratories</subject><subject>Large scale integration</subject><subject>Pins</subject><subject>Timing</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>0780357531</isbn><isbn>9780780357532</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotz7tOwzAUgGGLi0Ra2BGTX8DBd_uMULVQKRJDs1eOfSyMIKniCMTbM5Tp3z7pJ-Re8FYIDo_99tC3AgBaz43VcEEaqZxnUhp-SVbcea6MM0pckUZwD0wZBTdkVesH55IbyRtiuumHTt84v2NIdMG60NNUxoWWseK8lGmkeZppjWFkQ6iY6PP-0N-S6xw-K979d0363bbfvLLu7WW_eepY8W5h0WqJMSajjbZOBTFAxiBkGlApsNoYqTMk8BhDwgDGKgCXvfQxCwtarcnDmS2IeDzN5SvMv8fzrPoDuZdFww</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Nakao, M.</creator><creator>Kobayashi, S.</creator><creator>Hatayama, K.</creator><creator>Iijima, K.</creator><creator>Terada, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>Low overhead test point insertion for scan-based BIST</title><author>Nakao, M. ; Kobayashi, S. ; Hatayama, K. ; Iijima, K. ; Terada, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-c642eccd5454673a1b9fea12dbe339645524f9d98ecadea9563997f828cf16943</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Added delay</topic><topic>Built-in self-test</topic><topic>Circuit faults</topic><topic>Circuit testing</topic><topic>Delay effects</topic><topic>Flip-flops</topic><topic>Laboratories</topic><topic>Large scale integration</topic><topic>Pins</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Nakao, M.</creatorcontrib><creatorcontrib>Kobayashi, S.</creatorcontrib><creatorcontrib>Hatayama, K.</creatorcontrib><creatorcontrib>Iijima, K.</creatorcontrib><creatorcontrib>Terada, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nakao, M.</au><au>Kobayashi, S.</au><au>Hatayama, K.</au><au>Iijima, K.</au><au>Terada, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low overhead test point insertion for scan-based BIST</atitle><btitle>International Test Conference 1999. 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| ispartof | International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), 1999, p.348-357 |
| issn | 1089-3539 2378-2250 |
| language | eng |
| recordid | cdi_ieee_primary_805649 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Added delay Built-in self-test Circuit faults Circuit testing Delay effects Flip-flops Laboratories Large scale integration Pins Timing |
| title | Low overhead test point insertion for scan-based BIST |
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