Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)

We present cross-layer exploration for architecting resilience, a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, and area) b...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2018-09, Vol.37 (9), p.1839-1852
Hauptverfasser:	Cheng, Eric, Mirkhani, Shahrzad, Szafaryn, Lukasz G., Chen-Yong Cher, Hyungmin Cho, Skadron, Kevin, Stan, Mircea R., Lilja, Klas, Abraham, Jacob A., Bose, Pradip, Mitra, Subhasish
Format:	Artikel
Sprache:	eng
Schlagworte:	Benchmark testing Circuits Computer architecture Core hardenability Cost engineering Cross-layer resilience Digital systems Energy costs Exploration Flip-flops Integrated circuit reliability Microprocessors Radiation effects Reliability engineering Resilience Single event upsets Soft errors Terrestrial environments
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