60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2017-10, Vol.52 (10), p.2576-2588
Hauptverfasser:	Chan, Chi-Hang, Zhu, Yan, Li, Cheng, Zhang, Wai-Hong, Ho, Iok-Meng, Wei, Lai, U, Seng-Pan, Martins, Rui Paulo
Format:	Artikel
Sprache:	eng
Schlagworte:	Analog to digital conversion Analog to digital converters Calibration Capacitors Circuit design CMOS Decoupling Error correction Noise levels Prototypes Reference buffer reference error calibration Registers Subtraction successive approximation register (SAR) analog-to-digital converter (ADC) Switches Switching System-on-chip threshold reconfigurable comparator Topology Transient analysis
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