Algorithm and architecture of a 1 V low power hearing instrument DSP
This paper presents a 1 V digital signal processor used in the Danalogic hearing aid manufactured by GN Danavox. The processor is the first general purpose programmable device used in behind-the-ear and in-the-ear hearing aid applications. It is integrated with memories, in a 0.5 /spl mu/m CMOS proc...
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| creator | Moller, F. Bisgaard, N. Melanson, J. |
| description | This paper presents a 1 V digital signal processor used in the Danalogic hearing aid manufactured by GN Danavox. The processor is the first general purpose programmable device used in behind-the-ear and in-the-ear hearing aid applications. It is integrated with memories, in a 0.5 /spl mu/m CMOS process with standard thresholds. At 2 MHz processing speed, the processor consumes 800 /spl mu/A from a single cell battery. Using a dual multiply-accumulate architecture, the processor executes a 256 point block floating-point FFT in just 2900 instruction cycles. |
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The processor is the first general purpose programmable device used in behind-the-ear and in-the-ear hearing aid applications. It is integrated with memories, in a 0.5 /spl mu/m CMOS process with standard thresholds. At 2 MHz processing speed, the processor consumes 800 /spl mu/A from a single cell battery. Using a dual multiply-accumulate architecture, the processor executes a 256 point block floating-point FFT in just 2900 instruction cycles.</description><identifier>ISBN: 158113133X</identifier><identifier>ISBN: 9781581131338</identifier><language>eng</language><publisher>IEEE</publisher><subject>Auditory system ; CMOS process ; CMOS technology ; Digital filters ; Digital signal processing ; Digital signal processors ; Hearing aids ; Instruments ; Read only memory ; Signal processing algorithms</subject><ispartof>Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. 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Using a dual multiply-accumulate architecture, the processor executes a 256 point block floating-point FFT in just 2900 instruction cycles.</description><subject>Auditory system</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Digital filters</subject><subject>Digital signal processing</subject><subject>Digital signal processors</subject><subject>Hearing aids</subject><subject>Instruments</subject><subject>Read only memory</subject><subject>Signal processing algorithms</subject><isbn>158113133X</isbn><isbn>9781581131338</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9yb0KwjAUQOGACP71BZzuCwgNabQdxSqOgiJuJdTbJtIk5Sal-PY6OHuWbzgTtuAy51xwIR4zloTwSr9JmWfFds7Kfdd6MlFbUO4JimptItZxIATfgAIOd-j8CL0fkUCjIuNaMC5EGiy6COX1smLTRnUBk59Ltj4db4fzxiBi1ZOxit7VriiylIu_8wMQlTPF</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Moller, F.</creator><creator>Bisgaard, N.</creator><creator>Melanson, J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1999</creationdate><title>Algorithm and architecture of a 1 V low power hearing instrument DSP</title><author>Moller, F. ; Bisgaard, N. ; Melanson, J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7994013</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Auditory system</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Digital filters</topic><topic>Digital signal processing</topic><topic>Digital signal processors</topic><topic>Hearing aids</topic><topic>Instruments</topic><topic>Read only memory</topic><topic>Signal processing algorithms</topic><toplevel>online_resources</toplevel><creatorcontrib>Moller, F.</creatorcontrib><creatorcontrib>Bisgaard, N.</creatorcontrib><creatorcontrib>Melanson, J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Moller, F.</au><au>Bisgaard, N.</au><au>Melanson, J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Algorithm and architecture of a 1 V low power hearing instrument DSP</atitle><btitle>Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)</btitle><stitle>LPE</stitle><date>1999</date><risdate>1999</risdate><spage>7</spage><epage>11</epage><pages>7-11</pages><isbn>158113133X</isbn><isbn>9781581131338</isbn><abstract>This paper presents a 1 V digital signal processor used in the Danalogic hearing aid manufactured by GN Danavox. The processor is the first general purpose programmable device used in behind-the-ear and in-the-ear hearing aid applications. It is integrated with memories, in a 0.5 /spl mu/m CMOS process with standard thresholds. At 2 MHz processing speed, the processor consumes 800 /spl mu/A from a single cell battery. Using a dual multiply-accumulate architecture, the processor executes a 256 point block floating-point FFT in just 2900 instruction cycles.</abstract><pub>IEEE</pub></addata></record> |
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| identifier | ISBN: 158113133X |
| ispartof | Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), 1999, p.7-11 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Auditory system CMOS process CMOS technology Digital filters Digital signal processing Digital signal processors Hearing aids Instruments Read only memory Signal processing algorithms |
| title | Algorithm and architecture of a 1 V low power hearing instrument DSP |
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