A 21-dBm I/Q Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology
This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D...
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| Veröffentlicht in: | IEEE transactions on microwave theory and techniques 2017-11, Vol.65 (11), p.4744-4757 |
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| creator | Gaber, Wagdy M. Wambacq, Piet Craninckx, Jan Ingels, Mark |
| description | This paper proposes the use of a high-power stacked output stage for a current-based in-phase/quadrature (I/Q) direct digital to RF modulator (DDRM) in bulk CMOS. The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (P SAT ) of 25 dBm and a peak output power (P out ) of 21 dBm at 1-GHz carrier frequency ( f c ). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (η sys ), respectively. In addition, it achieves 11.5% η sys with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average P out , and at 1-GHz f c with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm). |
| doi_str_mv | 10.1109/TMTT.2017.2707415 |
| format | Article |
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The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (P SAT ) of 25 dBm and a peak output power (P out ) of 21 dBm at 1-GHz carrier frequency ( f c ). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (η sys ), respectively. In addition, it achieves 11.5% η sys with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. 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The main nonlinearities associated with implementing the stacked transistor on top of the I/Q DDRM are easily compensated by a simple 2-D digital predistortion. A prototype implemented in 28-nm bulk CMOS achieves a saturated output power (P SAT ) of 25 dBm and a peak output power (P out ) of 21 dBm at 1-GHz carrier frequency ( f c ). Their corresponding efficiencies are 45% power added efficiency and 33% system efficiency (η sys ), respectively. In addition, it achieves 11.5% η sys with a -30.5-dB error vector magnitude when transmitting a 40-MHz 64 quadrature amplitude modulation wireless local area network (WLAN) signal. The WLAN signal is transmitted at 12-dBm average P out , and at 1-GHz f c with 8.73-dB peak to average power ratio (peak Pout of 20.73 dBm).</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TMTT.2017.2707415</doi><tpages>14</tpages><orcidid>https://orcid.org/0000-0003-0522-0144</orcidid></addata></record> |
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| subjects | <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">I/Q Carrier frequencies CMOS CMOS technology Digital TXs direct digital to RF modulator (DDRM) efficiency high peak to average power ratio (PAPR) Linearity Local area networks Modulation nanometer CMOS Power efficiency Power generation Quadrature amplitude modulation Radio frequency Silicon stacked Substrates Transistors Wireless networks |
| title | A 21-dBm I/Q Digital Transmitter Using Stacked Output Stage in 28-nm Bulk CMOS Technology |
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