$V -band \times 8 Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process$

V -band \times 8 Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process

This paper proposes a V-band ×8 frequency multiplier for 60-GHz wireless communication systems using 65-nm CMOS technology. The ×8 frequency multiplier consists of three stages of amplifiers and three stages of doublers. The second and fifth stages of the frequency multiplier are balanced structures...

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Veröffentlicht in:	IEEE microwave and wireless components letters 2017-05, Vol.27 (5), p.506-508
Hauptverfasser:	Kim, Jae-Sun, Oh, Hyun-Myung, Byeon, Chul Woo, Son, Ju Ho, Lee, Jeong Ho, Lee, Jooseok, Kim, Choul-Young
Format:	Artikel
Sprache:	eng
Schlagworte:	65-nm CMOS CMOS frequency multiplier CMOS process doubler Harmonic analysis harmonic suppression Harmonics suppression Periodic structures Power demand Power generation V-band Wireless communication
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