Small VCO-Gain Variation Adding a Bias-Shifted Inversion-Mode MOS Varactor

This letter proposes a small voltage-controlled oscillator (VCO)-gain variation (AKVCO) technique using the capacitance-slope change of the varactor, which is achieved by adding a bias-shifted inversion-mode MOS varactor in parallel with a conventional accumulation-mode MOS varactor. This technique...

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Veröffentlicht in:	IEEE microwave and wireless components letters 2017-04, Vol.27 (4), p.395-397
Hauptverfasser:	Lim, Chang-Woo, Noh, Hong-Yeoul, Yun, Tae-Yeoul
Format:	Artikel
Sprache:	eng
Schlagworte:	Bias Capacitance CMOS Electric potential Figure of merit Inversion-mode MOS (I-MOS) varactor Phase locked loops Phase noise Tuning Varactors VCO-gain variation (ΔKVCO) Voltage controlled oscillators voltage-controlled oscillator (VCO) gain (KVCO)
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container_title	IEEE microwave and wireless components letters
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creator	Lim, Chang-Woo Noh, Hong-Yeoul Yun, Tae-Yeoul
description	This letter proposes a small voltage-controlled oscillator (VCO)-gain variation (AKVCO) technique using the capacitance-slope change of the varactor, which is achieved by adding a bias-shifted inversion-mode MOS varactor in parallel with a conventional accumulation-mode MOS varactor. This technique is investigated via theoretical analysis, which is confirmed by simulation and measurement. The proposed VCO shows a phase noise of -116.4 dBc/Hz at a 1-MHz offset frequency at 2.36 GHz, a figure of merit of -185 dBc/Hz, and a AKVCO of less than 8.6% over a frequency tuning range from 1.73 to 2.36 GHz while consuming 0.76 mW from a 0.8-V supply voltage. It was implemented using a 110-nm CMOS process with a chip area of 0.95 mm 2 .
doi_str_mv	10.1109/LMWC.2017.2678431
format	Article
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This technique is investigated via theoretical analysis, which is confirmed by simulation and measurement. The proposed VCO shows a phase noise of -116.4 dBc/Hz at a 1-MHz offset frequency at 2.36 GHz, a figure of merit of -185 dBc/Hz, and a AKVCO of less than 8.6% over a frequency tuning range from 1.73 to 2.36 GHz while consuming 0.76 mW from a 0.8-V supply voltage. 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This technique is investigated via theoretical analysis, which is confirmed by simulation and measurement. The proposed VCO shows a phase noise of -116.4 dBc/Hz at a 1-MHz offset frequency at 2.36 GHz, a figure of merit of -185 dBc/Hz, and a AKVCO of less than 8.6% over a frequency tuning range from 1.73 to 2.36 GHz while consuming 0.76 mW from a 0.8-V supply voltage. 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This technique is investigated via theoretical analysis, which is confirmed by simulation and measurement. The proposed VCO shows a phase noise of -116.4 dBc/Hz at a 1-MHz offset frequency at 2.36 GHz, a figure of merit of -185 dBc/Hz, and a AKVCO of less than 8.6% over a frequency tuning range from 1.73 to 2.36 GHz while consuming 0.76 mW from a 0.8-V supply voltage. It was implemented using a 110-nm CMOS process with a chip area of 0.95 mm 2 .</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LMWC.2017.2678431</doi><tpages>3</tpages><orcidid>https://orcid.org/0000-0003-3470-5693</orcidid></addata></record>
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subjects	Bias Capacitance CMOS Electric potential Figure of merit Inversion-mode MOS (I-MOS) varactor Phase locked loops Phase noise Tuning Varactors VCO-gain variation (ΔKVCO) Voltage controlled oscillators voltage-controlled oscillator (VCO) gain (KVCO)
title	Small VCO-Gain Variation Adding a Bias-Shifted Inversion-Mode MOS Varactor
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