Converting a 64 b PowerPC processor from CMOS bulk to SOI technology
A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI...
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| creator | Allen, D. Behrends, D. Stanisic, B. |
| description | A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI. |
| doi_str_mv | 10.1109/DAC.1999.782211 |
| format | Conference Proceeding |
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Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</description><identifier>ISBN: 1581130929</identifier><identifier>ISBN: 9781581130928</identifier><identifier>DOI: 10.1109/DAC.1999.782211</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit noise ; Circuit synthesis ; CMOS logic circuits ; CMOS process ; CMOS technology ; Copper ; Design automation ; Logic arrays ; Silicon on insulator technology ; Timing</subject><ispartof>Proceedings 1999 Design Automation Conference (Cat. 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The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</description><subject>Circuit noise</subject><subject>Circuit synthesis</subject><subject>CMOS logic circuits</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Copper</subject><subject>Design automation</subject><subject>Logic arrays</subject><subject>Silicon on insulator technology</subject><subject>Timing</subject><isbn>1581130929</isbn><isbn>9781581130928</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssKgkAUQAci6OU6aHV_IJvre5YxFrUIBduLymiWOjJjRX9fUOvO5izO5hCyRGoiUrYJt9xExpjpB5aFOCIzdANEmzKLTYih9ZV-cKnHfGdKQi67h1BD3VWQgedADrF8ChVz6JUshNZSQalkC_wUJZDfmxsMEpLoCIMoLp1sZPVakHGZNVoYP8_Jar8788O6FkKkvarbTL3S74_9N74BGpc3mg</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Allen, D.</creator><creator>Behrends, D.</creator><creator>Stanisic, B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</title><author>Allen, D. ; Behrends, D. ; Stanisic, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_7822113</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Circuit noise</topic><topic>Circuit synthesis</topic><topic>CMOS logic circuits</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Copper</topic><topic>Design automation</topic><topic>Logic arrays</topic><topic>Silicon on insulator technology</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Allen, D.</creatorcontrib><creatorcontrib>Behrends, D.</creatorcontrib><creatorcontrib>Stanisic, B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Allen, D.</au><au>Behrends, D.</au><au>Stanisic, B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Converting a 64 b PowerPC processor from CMOS bulk to SOI technology</atitle><btitle>Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)</btitle><stitle>DAC</stitle><date>1999</date><risdate>1999</risdate><spage>892</spage><epage>897</epage><pages>892-897</pages><isbn>1581130929</isbn><isbn>9781581130928</isbn><abstract>A 550 MHz 64 b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS. Both the design and the associated CAD methodology (point tools, flow, and models) were modified to handle demands specific to SOI technology. The challenge was to improve the cycle time by adapting the circuit design, timing, and chip integration methodologies to accommodate effects unique to SOI.</abstract><pub>IEEE</pub><doi>10.1109/DAC.1999.782211</doi></addata></record> |
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| identifier | ISBN: 1581130929 |
| ispartof | Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1999, p.892-897 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit noise Circuit synthesis CMOS logic circuits CMOS process CMOS technology Copper Design automation Logic arrays Silicon on insulator technology Timing |
| title | Converting a 64 b PowerPC processor from CMOS bulk to SOI technology |
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