An efficient data path synthesis algorithm for behavioral-level power optimization
This paper presents a new data path synthesis algorithm which solves two important design problems: scheduling and allocation with power minimization as a key design objective. Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for s...
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| creator | Chaeryung Park Taewhan Park Liu, C.L. |
| description | This paper presents a new data path synthesis algorithm which solves two important design problems: scheduling and allocation with power minimization as a key design objective. Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for solving the problem. We then develop a stepwise approximation algorithm utilizing the formulation to carry out the scheduling and allocation in an integrated fashion. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption. |
| doi_str_mv | 10.1109/ISCAS.1999.777861 |
| format | Conference Proceeding |
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Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for solving the problem. We then develop a stepwise approximation algorithm utilizing the formulation to carry out the scheduling and allocation in an integrated fashion. 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Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for solving the problem. We then develop a stepwise approximation algorithm utilizing the formulation to carry out the scheduling and allocation in an integrated fashion. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption.</description><subject>Algorithm design and analysis</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Computer science</subject><subject>Energy consumption</subject><subject>Flow graphs</subject><subject>Linear programming</subject><subject>Processor scheduling</subject><subject>Scheduling algorithm</subject><subject>Turning</subject><isbn>9780780354715</isbn><isbn>0780354710</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKxDAYhQMiKGMfQFd5gdbE3JplKV4GBgRH10Pa_LGRtilJGBmf3sLM4cDZfXwHoXtKKkqJftzu22ZfUa11pZSqJb1ChVY1WcsEV1TcoCKlH7KGC6KpvEUfzYzBOd97mDO2Jhu8mDzgdJrzAMknbMbvEH0eJuxCxB0M5uhDNGM5whFGvIRfiDgs2U_-z2Qf5jt07cyYoLjsBn29PH-2b-Xu_XXbNrvSU8JzqXvZaeCaOCu5ZryXzKi-F5SLVVY4kEx3rK6V6piVFmpHjNT2aVV3ne0d26CHM9cDwGGJfjLxdDgfZ_8U40_a</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Chaeryung Park</creator><creator>Taewhan Park</creator><creator>Liu, C.L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>An efficient data path synthesis algorithm for behavioral-level power optimization</title><author>Chaeryung Park ; Taewhan Park ; Liu, C.L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-9c6b9e490fd64934c63a7cc51453545fe639b38877b3d6de8f0a69d2045fbdcf3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Algorithm design and analysis</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Computer science</topic><topic>Energy consumption</topic><topic>Flow graphs</topic><topic>Linear programming</topic><topic>Processor scheduling</topic><topic>Scheduling algorithm</topic><topic>Turning</topic><toplevel>online_resources</toplevel><creatorcontrib>Chaeryung Park</creatorcontrib><creatorcontrib>Taewhan Park</creatorcontrib><creatorcontrib>Liu, C.L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chaeryung Park</au><au>Taewhan Park</au><au>Liu, C.L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An efficient data path synthesis algorithm for behavioral-level power optimization</atitle><btitle>1999 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1999</date><risdate>1999</risdate><volume>1</volume><spage>294</spage><epage>297 vol.1</epage><pages>294-297 vol.1</pages><isbn>9780780354715</isbn><isbn>0780354710</isbn><abstract>This paper presents a new data path synthesis algorithm which solves two important design problems: scheduling and allocation with power minimization as a key design objective. Based on the observations found in prior work on synthesis for low power we derive an integer programming formulation for solving the problem. We then develop a stepwise approximation algorithm utilizing the formulation to carry out the scheduling and allocation in an integrated fashion. Our experimentation results show that the algorithm is quite effective, producing designs with significant savings in power consumption.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1999.777861</doi></addata></record> |
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| identifier | ISBN: 9780780354715 |
| ispartof | 1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.1, p.294-297 vol.1 |
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| language | eng |
| recordid | cdi_ieee_primary_777861 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Circuits Clocks Computer science Energy consumption Flow graphs Linear programming Processor scheduling Scheduling algorithm Turning |
| title | An efficient data path synthesis algorithm for behavioral-level power optimization |
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