A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers
This paper describes the implementation of a 5th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 /spl mu/m CMOS process and operates at 3.3 V supply volta...
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| creator | Westesson, E. Sundstrom, L. |
| description | This paper describes the implementation of a 5th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 /spl mu/m CMOS process and operates at 3.3 V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB. |
| doi_str_mv | 10.1109/ISCAS.1999.777839 |
| format | Conference Proceeding |
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The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 /spl mu/m CMOS process and operates at 3.3 V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB.</description><identifier>ISBN: 9780780354715</identifier><identifier>ISBN: 0780354710</identifier><identifier>DOI: 10.1109/ISCAS.1999.777839</identifier><language>eng</language><publisher>IEEE</publisher><subject>Baseband ; CMOS process ; Energy consumption ; Performance evaluation ; Polynomials ; Power amplifiers ; Radio frequency ; Radiofrequency amplifiers ; Semiconductor device measurement ; Voltage</subject><ispartof>1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.1, p.206-209 vol.1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/777839$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/777839$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Westesson, E.</creatorcontrib><creatorcontrib>Sundstrom, L.</creatorcontrib><title>A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers</title><title>1999 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper describes the implementation of a 5th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 /spl mu/m CMOS process and operates at 3.3 V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB.</description><subject>Baseband</subject><subject>CMOS process</subject><subject>Energy consumption</subject><subject>Performance evaluation</subject><subject>Polynomials</subject><subject>Power amplifiers</subject><subject>Radio frequency</subject><subject>Radiofrequency amplifiers</subject><subject>Semiconductor device measurement</subject><subject>Voltage</subject><isbn>9780780354715</isbn><isbn>0780354710</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkN1KxDAUhAMiKGsfQK_yAq3J9ic9l6VYLawsWL1e8nOCkbYpaUHXpzewDgNnbuaDM4Tcc5ZxzuCxH9pmyDgAZEKIOocrkoCoWXReFoKXNyRZ1y8WVZQMeHVLbEO1n5YRf-jix_PsJydHugQ0bt182DBQ_ekW6mbavh4Han2gSq6o5GxozH1HRzejDO5Xbs7P1Fv61kXWd2zKCHbWYVjvyLWV44rJ_92Rj-7pvX1JD8fnvm0OqeOs2FKjjFBgpGEFs1CzSqlS50xbVYOxpoJqD7oCWaCoSyhRC6FQabM3aET8NN-RhwvXIeJpCW6S4Xy6jJH_ARdKVwg</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Westesson, E.</creator><creator>Sundstrom, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers</title><author>Westesson, E. ; Sundstrom, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-dbd7b9dad040f9806bb5c30cfb89dfd69629c69a4e78595ec77bebcd2ded79783</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Baseband</topic><topic>CMOS process</topic><topic>Energy consumption</topic><topic>Performance evaluation</topic><topic>Polynomials</topic><topic>Power amplifiers</topic><topic>Radio frequency</topic><topic>Radiofrequency amplifiers</topic><topic>Semiconductor device measurement</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Westesson, E.</creatorcontrib><creatorcontrib>Sundstrom, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Westesson, E.</au><au>Sundstrom, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers</atitle><btitle>1999 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1999</date><risdate>1999</risdate><volume>1</volume><spage>206</spage><epage>209 vol.1</epage><pages>206-209 vol.1</pages><isbn>9780780354715</isbn><isbn>0780354710</isbn><abstract>This paper describes the implementation of a 5th order complex polynomial predistorter chip in CMOS for linearization of RF power amplifiers. The architecture chosen allows operation either at baseband or IF. The chip was implemented in a 0.8 /spl mu/m CMOS process and operates at 3.3 V supply voltage with 60 mW power consumption. The special architecture of the polynomial predistorter is exploited to reduce the complexity and current consumption of individual blocks. Two-tone measurements performed at an IF of 200 MHz demonstrates that third order intermodulation products can be suppressed by more than 30 dB.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1999.777839</doi></addata></record> |
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| identifier | ISBN: 9780780354715 |
| ispartof | 1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999, Vol.1, p.206-209 vol.1 |
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| language | eng |
| recordid | cdi_ieee_primary_777839 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Baseband CMOS process Energy consumption Performance evaluation Polynomials Power amplifiers Radio frequency Radiofrequency amplifiers Semiconductor device measurement Voltage |
| title | A complex polynomial predistorter chip in CMOS for baseband or IF linearization of RF power amplifiers |
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