Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards

We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yhonkyong Choi, Rim, C.S.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Benchmark testing Circuit testing Circuit topology Computer science Field programmable gate arrays Integrated circuit interconnections Pins Printed circuits Quadratic programming Routing
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