Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards
We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete...
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| creator | Yhonkyong Choi Rim, C.S. |
| description | We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete their routing and to minimize the I/O pins used. We also describe a heuristic method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the average reduction of the I/O pins used are up to 18% compared to the previous method for all the benchmark circuits tested. |
| doi_str_mv | 10.1109/CICC.1999.777346 |
| format | Conference Proceeding |
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Experimental results show that our method generates the partitions in which the average reduction of the I/O pins used are up to 18% compared to the previous method for all the benchmark circuits tested.</description><subject>Benchmark testing</subject><subject>Circuit testing</subject><subject>Circuit topology</subject><subject>Computer science</subject><subject>Field programmable gate arrays</subject><subject>Integrated circuit interconnections</subject><subject>Pins</subject><subject>Printed circuits</subject><subject>Quadratic programming</subject><subject>Routing</subject><isbn>9780780354432</isbn><isbn>0780354435</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1999</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01LxDAYhAMiKGvv4il_oPVNkzTNUYMfCwteFI_LmzQtkbapaXvYf29ldxiYy_AwQ8g9g4Ix0I9mb0zBtNaFUoqL6opkWtWwmUsheHlDsnn-gU1CiroUt-TbhOTWsNAJ0xKWEMcwdtSe6O-KTcIlOPocY-9xpFOKXcJh-C-0MdHkXRzb0K0Jbe-pu4BsxNTMd-S6xX722SV35Ov15dO854ePt715OuSBgVhywawEBa3EuuTbykYCd1Zb75jktaxbFA2gqsAq5b2qGnCicqBLz73eLvAdeThzg_f-OKUwYDodz-_5H52kUNY</recordid><startdate>1999</startdate><enddate>1999</enddate><creator>Yhonkyong Choi</creator><creator>Rim, C.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>1999</creationdate><title>Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards</title><author>Yhonkyong Choi ; Rim, C.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-41b5070f5a823803d503cb9bec153858fa4d0a760b77ee76d0c46c092e3e95483</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Benchmark testing</topic><topic>Circuit testing</topic><topic>Circuit topology</topic><topic>Computer science</topic><topic>Field programmable gate arrays</topic><topic>Integrated circuit interconnections</topic><topic>Pins</topic><topic>Printed circuits</topic><topic>Quadratic programming</topic><topic>Routing</topic><toplevel>online_resources</toplevel><creatorcontrib>Yhonkyong Choi</creatorcontrib><creatorcontrib>Rim, C.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yhonkyong Choi</au><au>Rim, C.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards</atitle><btitle>Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)</btitle><stitle>CICC</stitle><date>1999</date><risdate>1999</risdate><spage>571</spage><epage>574</epage><pages>571-574</pages><isbn>9780780354432</isbn><isbn>0780354435</isbn><abstract>We propose a new quadratic Boolean programming problem formulation to partition a circuit for FPGA based reconfigurable circuit boards in which the routing topology among IC chips are predetermined. Nets passing through IC chips in their interconnections are considered in the formulation to complete their routing and to minimize the I/O pins used. We also describe a heuristic method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the average reduction of the I/O pins used are up to 18% compared to the previous method for all the benchmark circuits tested.</abstract><pub>IEEE</pub><doi>10.1109/CICC.1999.777346</doi><tpages>4</tpages></addata></record> |
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| identifier | ISBN: 9780780354432 |
| ispartof | Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), 1999, p.571-574 |
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| language | eng |
| recordid | cdi_ieee_primary_777346 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Benchmark testing Circuit testing Circuit topology Computer science Field programmable gate arrays Integrated circuit interconnections Pins Printed circuits Quadratic programming Routing |
| title | Circuit partitioning by quadratic Boolean programming for reconfigurable circuit boards |
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