Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs

In interposer-based 2.5-D integrated circuits, the passive silicon interposer is the least expensive component in the chip. Thus, it is desirable to test the interposer before bonding to ensure that more expensive and defect-free dies are not stacked on a faulty interposer. We present an efficient m...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2017-08, Vol.36 (8), p.1406-1419
Hauptverfasser:	Ran Wang, Zipeng Li, Kannan, Sukeshwar, Chakrabarty, Krishnendu
Format:	Artikel
Sprache:	eng
Schlagworte:	25-D IC Algorithm design and analysis Algorithms Architecture Assembly Computer simulation Defects Dies e-fuse Fuses Industries Integrated circuit interconnections Integrated circuits Interconnections prebond testing Silicon silicon interposer Stacking test-path design Testing Through-silicon vias
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