Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM
The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is...
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| Veröffentlicht in: | IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2017-10, Vol.64 (10), p.1147-1151 |
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| container_title | IEEE transactions on circuits and systems. II, Express briefs |
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| creator | Yun, Seong Jin Yun, Jeong Seok Kim, Yong Sin |
| description | The performance of switching devices such as display driver ICs is degraded by large power supply noise at switching frequencies from a few hundreds of kilohertz to a few megahertz. In order to minimize the power supply noise, a low-dropout (LDO) regulator with higher power supply rejection (PSR) is essential. In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a 0.18 μm CMOS. Measurement results show that the proposed LDO regulator achieves -76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF. |
| doi_str_mv | 10.1109/TCSII.2016.2628965 |
| format | Article |
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Measurement results show that the proposed LDO regulator achieves -76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.</description><subject>Capacitance</subject><subject>Capacitors</subject><subject>Logic gates</subject><subject>Low-dropout (LDO) regulator</subject><subject>negative capacitance</subject><subject>Power supplies</subject><subject>power supply rejection (PSR)</subject><subject>Regulators</subject><subject>Shock absorbers</subject><subject>Voltage control</subject><issn>1549-7747</issn><issn>1558-3791</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kNFKwzAUhoMoOKcvoDd5gdaTkzZpwJtZNy1UKtu8LmmTzErdRjMF38BrH9EnsXXDq_PDz_fDdwi5ZBAyBup6mS6yLERgIkSBiRLxERmxOE4CLhU7HnKkAikjeUrOvH8FQAUcR-Qm1dvWek_zu4LO7eq91btNRyf1S2M_mvWK_nx9S0HNLX1azKleG6pEyKnzdFY8npMTp1tvLw53TJ5n02X6EOTFfZZO8qBGIXcBR80T5RwKUYONEWtlhKuU7mtrZGUYamUAVAxJZUwla0AtYrCV0JGRko8J7nfrbuN9Z1257Zo33X2WDMrBv_zzLwf_8uDfQ1d7qLHW_gP9C6JICf4LuVZVBw</recordid><startdate>201710</startdate><enddate>201710</enddate><creator>Yun, Seong Jin</creator><creator>Yun, Jeong Seok</creator><creator>Kim, Yong Sin</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0002-6177-1496</orcidid></search><sort><creationdate>201710</creationdate><title>Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM</title><author>Yun, Seong Jin ; Yun, Jeong Seok ; Kim, Yong Sin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c267t-32a389ff266c0e522c9d6fb9ac26ed7bd12a9d009508bddb7c02a650eb6a4d773</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Capacitance</topic><topic>Capacitors</topic><topic>Logic gates</topic><topic>Low-dropout (LDO) regulator</topic><topic>negative capacitance</topic><topic>Power supplies</topic><topic>power supply rejection (PSR)</topic><topic>Regulators</topic><topic>Shock absorbers</topic><topic>Voltage control</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yun, Seong Jin</creatorcontrib><creatorcontrib>Yun, Jeong Seok</creatorcontrib><creatorcontrib>Kim, Yong Sin</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on circuits and systems. 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In this brief, a capless LDO regulator with a negative capacitance circuit and voltage damper is proposed for enhancing PSR and figure of merit (FOM), respectively, in switching devices. The proposed LDO regulator is fabricated in a 0.18 μm CMOS. Measurement results show that the proposed LDO regulator achieves -76 dB PSR at 1 MHz and 96.3 fs FOM with a total on-chip capacitance of as small as 12.7 pF.</abstract><pub>IEEE</pub><doi>10.1109/TCSII.2016.2628965</doi><tpages>5</tpages><orcidid>https://orcid.org/0000-0002-6177-1496</orcidid></addata></record> |
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| subjects | Capacitance Capacitors Logic gates Low-dropout (LDO) regulator negative capacitance Power supplies power supply rejection (PSR) Regulators Shock absorbers Voltage control |
| title | Capless LDO Regulator Achieving −76 dB PSR and 96.3 fs FOM |
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