Yield modeling for majority voting based defect-tolerant VLSI circuits

A yield model is developed for generalized N-tuple modular redundancy (NMR) based defect-tolerant designs. The yield model is both mathematical and simulation based where the simulation portion uses a random multiple fault injection simulation procedure while the mathematical portion accounts for de...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Stroud, C.E.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit faults Circuit simulation Fabrication Integrated circuit yield Mathematical model Nuclear magnetic resonance Redundancy Semiconductor device modeling Very large scale integration Voting
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