FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency

Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2017-07, Vol.36 (7), p.1167-1180
Hauptverfasser:	Guo, Jie, Wen, Wujie, Hu, Jingtong, Wang, Danghui, Li, Hai, Chen, Yiran
Format:	Artikel
Sprache:	eng
Schlagworte:	Bit error rate Bit error rate (BER) Error correction codes Interference Logic gates low density parity check (LDPC) NAND flash noise margin Parity check codes read latency Reliability Sensors
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