An analytical delay model for SRAM-based FPGA interconnections

In an SRAM-based FPGA, MOS transistors connect wire segments to construct interconnections between CLBs, resulting in large and unpredictable path delays. So it is necessary to be able to estimate interconnection delays quickly and accurately in order that performance-driven layout and analysis algo...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Zhou Feng, Huang Zhijun, Tong Jiarong, Tang Pushan
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Algorithm design and analysis Analytical models Delay estimation Field programmable gate arrays MOSFETs Optimization methods Performance analysis SPICE Voltage Wire
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