A 300 Mb/s BiCMOS disk drive channel with adaptive analog equalizer
This complete disk drive read-write channel device combines the functions of channel equalization with analog Nyquist filtering. This chip includes circuitry performing the following read channel functions: Viterbi sequence detection; 24/25 rate coding; synchronous digital servo processing; write pr...
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| creator | Bishop, A. Chan, I. Aronson, S. Moran, P. Hen, K. Cheng, R. Fitzpatrick, K.K. Stander, J. Chik, R. Kshonze, K. Aliahmad, M. Ngai, J. He, H. daVeiga, E. Bolte, P. Krasuk, C. Cerqua, B. Brown, R. Ziperovich, P. Fisher, K. |
| description | This complete disk drive read-write channel device combines the functions of channel equalization with analog Nyquist filtering. This chip includes circuitry performing the following read channel functions: Viterbi sequence detection; 24/25 rate coding; synchronous digital servo processing; write pre-compensation; clock synthesis; and support for multiple power modes. The channel performs maximum likelihood sequence detection to a new partial response target optimized for channel densities in the range 1.8-3.0b per PW50. Additional features of the chip include: two-stage thermal asperity correction; non-linear MR asymmetry correction; on-chip quality monitoring; dual mode-6b in data mode and 7b in servo mode-analog to digital converter (ADC); gain-insensitive zerophase restart circuitry; as well as analog and digital test features. |
| doi_str_mv | 10.1109/ISSCC.1999.759090 |
| format | Conference Proceeding |
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Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278)</btitle><stitle>ISSCC</stitle><date>1999</date><risdate>1999</risdate><spage>46</spage><epage>49</epage><pages>46-49</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9780780351264</isbn><isbn>0780351266</isbn><abstract>This complete disk drive read-write channel device combines the functions of channel equalization with analog Nyquist filtering. This chip includes circuitry performing the following read channel functions: Viterbi sequence detection; 24/25 rate coding; synchronous digital servo processing; write pre-compensation; clock synthesis; and support for multiple power modes. The channel performs maximum likelihood sequence detection to a new partial response target optimized for channel densities in the range 1.8-3.0b per PW50. Additional features of the chip include: two-stage thermal asperity correction; non-linear MR asymmetry correction; on-chip quality monitoring; dual mode-6b in data mode and 7b in servo mode-analog to digital converter (ADC); gain-insensitive zerophase restart circuitry; as well as analog and digital test features.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.1999.759090</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.46-49 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_759090 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | BiCMOS integrated circuits Circuit synthesis Circuit testing Clocks Disk drives Equalizers Filtering Maximum likelihood detection Servomechanisms Viterbi algorithm |
| title | A 300 Mb/s BiCMOS disk drive channel with adaptive analog equalizer |
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