Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems
Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding sche...
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Veröffentlicht in: | IEEE transactions on multi-scale computing systems 2016-10, Vol.2 (4), p.265-276 |
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creator | Zhao, Chenyuan Wysocki, Bryant T. Thiem, Clare D. McDonald, Nathan R. Li, Jialing Liu, Lingjia Yi, Yang |
description | Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding schemes are discussed. Two novel temporal encoding schemes, parallel and iteration, are presented. The power consumption of the encoder has been significantly reduced by combing the iteration encoding and low sampling rate in advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both the simulation and measurement results show the accuracy and efficiency of the proposed encoding circuits. The proposed iteration encoder has immediate applicability as a general purpose input encoder for a reservoir computing system. |
doi_str_mv | 10.1109/TMSCS.2016.2607164 |
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One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding schemes are discussed. Two novel temporal encoding schemes, parallel and iteration, are presented. The power consumption of the encoder has been significantly reduced by combing the iteration encoding and low sampling rate in advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both the simulation and measurement results show the accuracy and efficiency of the proposed encoding circuits. The proposed iteration encoder has immediate applicability as a general purpose input encoder for a reservoir computing system.</description><subject>Biomembranes</subject><subject>CMOS</subject><subject>CMOS technology</subject><subject>Encoding</subject><subject>iteration scheme</subject><subject>Iterative methods</subject><subject>Mathematical model</subject><subject>Neuromorphics</subject><subject>Neurons</subject><subject>parallel scheme</subject><subject>rate encoding</subject><subject>Semiconductor device modeling</subject><subject>Temporal encoding</subject><issn>2332-7766</issn><issn>2332-7766</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpNkMtOwzAURC0EEhX0B2DjH0i59m3tZIlCeEgFFinryHGui6F5yE4X_XtaWiFWM4s5sziM3QiYCQHZ3eq1zMuZBKFmUoEWan7GJhJRJlordf6vX7JpjF8A-ykA6sWElUVHYb3jhXPeeupGXg7-23drvqJ26IPZ8KKzfUOBP1D06467PvA32oa-7cPw6S3P-3bYjgek3MWR2njNLpzZRJqe8op9PBar_DlZvj-95PfLxCLqMXECYVGj1ULXEoV04Mg0qGVmjEvTpiarEQltkxrharDzWmUAGVFtalQpXjF5_LWhjzGQq4bgWxN2lYDqYKb6NVMdzFQnM3vo9gh5IvoD9EIhgsYfl-phQg</recordid><startdate>20161001</startdate><enddate>20161001</enddate><creator>Zhao, Chenyuan</creator><creator>Wysocki, Bryant T.</creator><creator>Thiem, Clare D.</creator><creator>McDonald, Nathan R.</creator><creator>Li, Jialing</creator><creator>Liu, Lingjia</creator><creator>Yi, Yang</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20161001</creationdate><title>Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems</title><author>Zhao, Chenyuan ; Wysocki, Bryant T. ; Thiem, Clare D. ; McDonald, Nathan R. ; Li, Jialing ; Liu, Lingjia ; Yi, Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c337t-f1305b3c717b2312f0fead3729aaf88dbec733e3cd8a1fb0c4b69009eebab3683</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Biomembranes</topic><topic>CMOS</topic><topic>CMOS technology</topic><topic>Encoding</topic><topic>iteration scheme</topic><topic>Iterative methods</topic><topic>Mathematical model</topic><topic>Neuromorphics</topic><topic>Neurons</topic><topic>parallel scheme</topic><topic>rate encoding</topic><topic>Semiconductor device modeling</topic><topic>Temporal encoding</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhao, Chenyuan</creatorcontrib><creatorcontrib>Wysocki, Bryant T.</creatorcontrib><creatorcontrib>Thiem, Clare D.</creatorcontrib><creatorcontrib>McDonald, Nathan R.</creatorcontrib><creatorcontrib>Li, Jialing</creatorcontrib><creatorcontrib>Liu, Lingjia</creatorcontrib><creatorcontrib>Yi, Yang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE transactions on multi-scale computing systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhao, Chenyuan</au><au>Wysocki, Bryant T.</au><au>Thiem, Clare D.</au><au>McDonald, Nathan R.</au><au>Li, Jialing</au><au>Liu, Lingjia</au><au>Yi, Yang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems</atitle><jtitle>IEEE transactions on multi-scale computing systems</jtitle><stitle>TMSCS</stitle><date>2016-10-01</date><risdate>2016</risdate><volume>2</volume><issue>4</issue><spage>265</spage><epage>276</epage><pages>265-276</pages><issn>2332-7766</issn><eissn>2332-7766</eissn><coden>ITMCFM</coden><abstract>Neuromorphic computing hardware has undergone a rapid development and progress in the past few years. One of the key components in neuromorphic computing systems is the neural encoder which transforms sensory information into spike trains. In this paper, both rate encoding and temporal encoding schemes are discussed. Two novel temporal encoding schemes, parallel and iteration, are presented. The power consumption of the encoder has been significantly reduced by combing the iteration encoding and low sampling rate in advanced complementary metal-oxide semiconductor (CMOS) nano-technology. Both the simulation and measurement results show the accuracy and efficiency of the proposed encoding circuits. The proposed iteration encoder has immediate applicability as a general purpose input encoder for a reservoir computing system.</abstract><pub>IEEE</pub><doi>10.1109/TMSCS.2016.2607164</doi><tpages>12</tpages></addata></record> |
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subjects | Biomembranes CMOS CMOS technology Encoding iteration scheme Iterative methods Mathematical model Neuromorphics Neurons parallel scheme rate encoding Semiconductor device modeling Temporal encoding |
title | Energy Efficient Spiking Temporal Encoder Design for Neuromorphic Computing Systems |
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