Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentral...

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Veröffentlicht in:	IEEE transactions on computers 2017-04, Vol.66 (4), p.702-716
Hauptverfasser:	Yasudo, Ryota, Matsutani, Hiroki, Koibuchi, Michihiro, Amano, Hideharu, Nakamura, Tadao
Format:	Artikel
Sprache:	eng
Schlagworte:	Computer architecture Delay Delays Interconnection networks Links Network topology networks-on-chip Optimization Pipeline processing Pipelines router architecture Routers System on chip Wires
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