Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers
As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentral...
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| Veröffentlicht in: | IEEE transactions on computers 2017-04, Vol.66 (4), p.702-716 |
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| container_title | IEEE transactions on computers |
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| creator | Yasudo, Ryota Matsutani, Hiroki Koibuchi, Michihiro Amano, Hideharu Nakamura, Tadao |
| description | As the number of cores on a chip increases, Networks-on-Chip (NoCs) that connect many cores would face long links to reduce hop counts. The long links become bottlenecks in terms of both energy and RC delays as technology advances. To alleviate the negative impact of long links, we propose decentralized routers for NoCs. A decentralized router consists of multiple submodules that are positioned on a link, and hence the long links are segmented. Furthermore, we illustrate the design of an entire network that uses decentralized routers to obtain a good tradeoff between hop counts and wire delays per hop. Decentralized routers are effective especially in high-radix topologies, such as the flattened butterfly, and energy-delay product is reduced by greater than 60 percent. As NoCs become larger and more complex, the benefit of the decentralized routers will become more significant. |
| doi_str_mv | 10.1109/TC.2016.2606597 |
| format | Article |
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| subjects | Computer architecture Delay Delays Interconnection networks Links Network topology networks-on-chip Optimization Pipeline processing Pipelines router architecture Routers System on chip Wires |
| title | Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers |
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