Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces

Many embedded applications process large amounts of data using regular computational kernels, amenable to acceleration by specialized hardware coprocessors. To reduce the significant design effort, the dedicated hardware may be automatically generated, usually starting from the application's so...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2017-01, Vol.25 (1), p.21-34
Hauptverfasser:	Paulino, Nuno M. C., Canas Ferreira, Joao, Cardoso, Joao M. P.
Format:	Artikel
Sprache:	eng
Schlagworte:	Acceleration Accelerators Binary acceleration Binary codes Computer architecture coprocessor Coprocessors Customization Field programmable gate arrays field-programmable gate array (FPGA) Floating point arithmetic Hardware Integers Kernel Kernels loop accelerator Microprocessors modulo-scheduling Parallel processing Pipelining (computers) Registers Runtime very long instruction word (VLIW) VLIW
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