A CMOS power-delay model for CAD optimization tools

A CMOS power-delay model for CAD optimization tools

The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered...

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Bibliographische Detailangaben
Hauptverfasser: Delaurenti, M., Masera, G., Piccinini, G., Ruo Roch, M., Zamboni, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
CMOS digital integrated circuits
CMOS technology
Delay estimation
Design optimization
Energy consumption
MOS devices
Semiconductor device modeling
Software libraries
Voltage
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Beschreibung
Zusammenfassung:The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization.
DOI:10.1109/LPD.1999.750405