A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications
A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-c...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 1991-03, Vol.26 (3), p.422-426 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 426 |
|---|---|
| container_issue | 3 |
| container_start_page | 422 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 26 |
| creator | Iranmanesh, A.A. Ilderem, V. Biswal, M. Bastani, B. |
| description | A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process.< > |
| doi_str_mv | 10.1109/4.75029 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref_RIE</sourceid><recordid>TN_cdi_ieee_primary_75029</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>75029</ieee_id><sourcerecordid>10_1109_4_75029</sourcerecordid><originalsourceid>FETCH-LOGICAL-c241t-bca0fd269ef75866e1de7b0e616a27ef97a301dd09c02fa6daaefca52fdb85753</originalsourceid><addsrcrecordid>eNo9kL1PwzAUxC0EEqUgZjZvTC7PbhwnY6koIBV1ACS26NV-bo3ypTgg5b-nJYjpdHc_3XCMXUuYSQn5XTIzGlR-wiZS60xIM_84ZRMAmYlcAZyzixg_DzZJMjlhtOAwywSvvnjF0X1jbcnxGOpdSaJtyoHfh-XL5pX3ZPd1Uza7gfum4_uw2wtHdQz9wLF2Y9BSdyir4wjHti2DxT40dbxkZx7LSFd_OmXvq4e35ZNYbx6fl4u1sCqRvdhaBO9UmpM3OktTko7MFiiVKSpDPjc4B-kc5BaUx9QhkreolXfbTBs9n7Lbcdd2TYwd-aLtQoXdUEgoju8USfH7zoG8GclARP_U2P0A3x9gNA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications</title><source>IEEE Electronic Library (IEL)</source><creator>Iranmanesh, A.A. ; Ilderem, V. ; Biswal, M. ; Bastani, B.</creator><creatorcontrib>Iranmanesh, A.A. ; Ilderem, V. ; Biswal, M. ; Bastani, B.</creatorcontrib><description>A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.75029</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; BiCMOS integrated circuits ; Bipolar transistors ; CMOS integrated circuits ; CMOS logic circuits ; CMOS process ; CMOS technology ; Logic arrays ; Metallization ; Standards development</subject><ispartof>IEEE journal of solid-state circuits, 1991-03, Vol.26 (3), p.422-426</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c241t-bca0fd269ef75866e1de7b0e616a27ef97a301dd09c02fa6daaefca52fdb85753</citedby><cites>FETCH-LOGICAL-c241t-bca0fd269ef75866e1de7b0e616a27ef97a301dd09c02fa6daaefca52fdb85753</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/75029$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27903,27904,54736</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/75029$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Iranmanesh, A.A.</creatorcontrib><creatorcontrib>Ilderem, V.</creatorcontrib><creatorcontrib>Biswal, M.</creatorcontrib><creatorcontrib>Bastani, B.</creatorcontrib><title>A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process.< ></description><subject>Application specific integrated circuits</subject><subject>BiCMOS integrated circuits</subject><subject>Bipolar transistors</subject><subject>CMOS integrated circuits</subject><subject>CMOS logic circuits</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Logic arrays</subject><subject>Metallization</subject><subject>Standards development</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1991</creationdate><recordtype>article</recordtype><recordid>eNo9kL1PwzAUxC0EEqUgZjZvTC7PbhwnY6koIBV1ACS26NV-bo3ypTgg5b-nJYjpdHc_3XCMXUuYSQn5XTIzGlR-wiZS60xIM_84ZRMAmYlcAZyzixg_DzZJMjlhtOAwywSvvnjF0X1jbcnxGOpdSaJtyoHfh-XL5pX3ZPd1Uza7gfum4_uw2wtHdQz9wLF2Y9BSdyir4wjHti2DxT40dbxkZx7LSFd_OmXvq4e35ZNYbx6fl4u1sCqRvdhaBO9UmpM3OktTko7MFiiVKSpDPjc4B-kc5BaUx9QhkreolXfbTBs9n7Lbcdd2TYwd-aLtQoXdUEgoju8USfH7zoG8GclARP_U2P0A3x9gNA</recordid><startdate>19910301</startdate><enddate>19910301</enddate><creator>Iranmanesh, A.A.</creator><creator>Ilderem, V.</creator><creator>Biswal, M.</creator><creator>Bastani, B.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>19910301</creationdate><title>A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications</title><author>Iranmanesh, A.A. ; Ilderem, V. ; Biswal, M. ; Bastani, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c241t-bca0fd269ef75866e1de7b0e616a27ef97a301dd09c02fa6daaefca52fdb85753</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Application specific integrated circuits</topic><topic>BiCMOS integrated circuits</topic><topic>Bipolar transistors</topic><topic>CMOS integrated circuits</topic><topic>CMOS logic circuits</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Logic arrays</topic><topic>Metallization</topic><topic>Standards development</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Iranmanesh, A.A.</creatorcontrib><creatorcontrib>Ilderem, V.</creatorcontrib><creatorcontrib>Biswal, M.</creatorcontrib><creatorcontrib>Bastani, B.</creatorcontrib><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Iranmanesh, A.A.</au><au>Ilderem, V.</au><au>Biswal, M.</au><au>Bastani, B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1991-03-01</date><risdate>1991</risdate><volume>26</volume><issue>3</issue><spage>422</spage><epage>426</epage><pages>422-426</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process.< ></abstract><pub>IEEE</pub><doi>10.1109/4.75029</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1991-03, Vol.26 (3), p.422-426 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_75029 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits BiCMOS integrated circuits Bipolar transistors CMOS integrated circuits CMOS logic circuits CMOS process CMOS technology Logic arrays Metallization Standards development |
| title | A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-26T19%3A54%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%200.8-%20mu%20m%20advanced%20single-poly%20BiCMOS%20technology%20for%20high-density%20and%20high-performance%20applications&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Iranmanesh,%20A.A.&rft.date=1991-03-01&rft.volume=26&rft.issue=3&rft.spage=422&rft.epage=426&rft.pages=422-426&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.75029&rft_dat=%3Ccrossref_RIE%3E10_1109_4_75029%3C/crossref_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=75029&rfr_iscdi=true |